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US 6,448,808 B2Granted
Interconnect structure for a programmable logic device
AssigneeXilinx, Inc.
InventorsSteven P. Young, Kamal Chaudhary, Trevor J. Bauer
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AssigneeXilinx, Inc.
InventorsSteven P. Young, Kamal Chaudhary, Trevor J. Bauer
Estimating the term…
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
An interconnect structure for a programmable logic device, the programmable logic device including a plurality of substantially identical tiles, each tile including a logic block, the interconnect structure in each tile comprising:
A method of designing an interconnect structure for a programmable logic device, the programmable logic device including a plurality of substantially identical tiles, each tile including a logic block, the method comprising:
Dependencies are inferred from the claim text.