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US 6,448,665 B1Granted
Semiconductor package and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsTakahito Nakazawa, Yoshiaki Sugizaki
Life of this patent
Estimating the term…
Abstract
In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are αs, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are αr, Er and Hr, respectively, the value R of (αr·Er·Hr)/(αs·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.
Claims15
A semiconductor device, comprising:
- a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area;
- a semiconductor chip having a first face and a second face, the semiconductor chip having at least a connecting terminal formed on the first face, and the semiconductor chip being mounted on the first area of the wiring substrate in a face-down type;
- at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor chip;
- and
- a sealing resin layer having a first face substantially in parallel with the first face of the wiring substrate and disposed on the first face of the wiring substrate so that the second face of the semiconductor chip being exposed, side faces of the semiconductor chip being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor chip being filled;
- wherein the first face of the wiring substrate is completely covered with the resin layer and a size of the first face of the resin layer is different from that of the first face of the wiring substrate, the thickness of the resin layer is in the range of 50 to 100% of that of the wiring substrate, the resin layer has a first portion filled in between the wiring substrate and the semiconductor element, and a second portion covering the semiconductor chip from above the second face of the semiconductor chip, and wherein a Young's modulus of the resin of the first portion is smaller than that of the resin of the second portion.
3 more elements
A semiconductor device, comprising:
- a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face;
- a semiconductor chip having a first face and a second face, the semiconductor chip having at least a connecting terminal formed on the first face, and the semiconductor chip being mounted on a first area of the wiring substrate in a face-down type;
- at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor chip;
- and
- a resin layer disposed on the first face of the wiring substrate so that the semiconductor chip is sealed;
- wherein, (αr·Er·Hr)/(αs·Es·Hs) is approximately 0.6 or more, where αr is a thermal expansion coefficient of the resin layer, Er is a Young's modulus of the resin layer, Hr is a thickness of the resin layer, αs is a thermal expansion coefficient of the wiring substrate, Es is a Young's modulus of the wiring substrate, and Hs is a thickness of the wiring substrate.
3 more elements
A semiconductor device, comprising:
- a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounding the first area, and at least a first connecting pad arranged in the first area;
- a semiconductor chip having a first face and a second face, the semiconductor chip having at least a connecting terminal formed on the first face, and the semiconductor chip being mounted on the first area of the wiring substrate in a face-down type;
- at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor chip;
- and
- a sealing resin layer having a first face substantially in parallel with thw first face of the wiring substrate and disposed on the first face of the wiring substrate so that the second face of the semiconductor chip being exposed, side faces of the semiconductor chip being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor chip being filled;
- wherein the first face of the wiring substrate is completely covered with the resin layer and a size of the first face of the resin layer is different from that of the first face of the wiring substrate, wherein the thickness of the resin layer is in a range of 50 to 100% of that of the wiring substrate,
- wherein the resin layer has a first portion filled in between the wiring substrate and the semiconductor chip and a second portion covering the semiconductor chip from above the second face of the semiconductor chip, the first portion including a first resin and the second portion including a second resin different from the first resin, and
- whereing a Young's modulus of the first resin is smaller than that of the second resin.
5 more elements
Dependencies are inferred from the claim text.