US 6,446,249 B1 · Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory

Abstract

A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Claims46

Dependent claims

An integrated circuit logic element for implementing reconfigurable logic comprising:

an input line that inputs a signal into the logic element;
a lookup table coupled to the input line that receives the inputted signal and outputs a first data on a first output line;
a programmable delay circuit that receives the first data on the first output line and a first clock signal, the delay circuit outputing a delayed first data, the delayed first data being the first data delayed by a selectable amount, the selectable amount being determined by said first clock signal, said programmable delay circuit being selectively activated;
a data latch coupled to the delay circuit that receives the delayed first data and outputs a second data on its output;
an output line that receives one of the first data, delayed first data, or the second data and passes it out of the logic element.

2 more elements

Dependencies are inferred from the claim text.

Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory

Life of this patent

Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory

Life of this patent

Abstract

Claims46