Automated method for testing cache
AssigneeTexas Instruments Incorporated
InventorsChristopher L. Mobley, Timothy D. Anderson, Charles L. Fuoco, Sanjive Agarwala
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AssigneeTexas Instruments Incorporated
InventorsChristopher L. Mobley, Timothy D. Anderson, Charles L. Fuoco, Sanjive Agarwala
Estimating the term…
A method generates a list of allowed states in a cache design by applying each input transaction sequentially to all found legal cache states. If application of an input transaction to a current search cache results in a new cache state, then this new cache state is added to the list of legal cache states and to a list of search cache states. This is repeated for all input transactions and all such found legal cache states. At the same time a sequence of input transactions reaching each new cache state is formed. This new sequence is the sequence of input transactions for the prior cache state and the current input transaction. The method generates a series of test sequences from the list of allowed states and their corresponding sequence of input transactions which are applied to the control logic cache design and to a reference memory. If the response of the control logic cache design fails to match the response of the reference memory, then a design fault is detected.
A method for testing a control logic cache design, comprising the steps of:
A method for determining all legal states of a control logic cache design, comprising the steps of:
Dependencies are inferred from the claim text.