Evaluation of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay

Abstract

An evaluation system for evaluating the suitability of a target technology library for use with an electronic design automation system that converts the target technology library into a scalable library having non-linear, gain-based delay models for estimating circuit delay. After a library analysis process executes, an internal scalable library is generated having a scalable cell model for each functional cell class of the target technology library. Internal characteristics of the scalable library are analyzed to determine whether or not the target technology library is suitable for generating a suitable scalable library. Suitable scalable libraries are used for gain-based structuring and mapping processes. The library evaluation processes uses several metrics to determine the suitability the target technology library. The first metric is the number of sizes metric and the second metric is the size consistency metric. The number of sizes metric is computed with respect to subsets (e.g., basic set and extended set) of the scalable cells identified within the scalable library. The number of sizes metric determines whether or not there are sufficient numbers of discrete cells within the cell clusters of the subsets. The size consistency metric examines the input pin capacitance ratios and the delay error amounts for discrete cells of the scalable library. An evaluation report is then compiled using the above metric information to grade library suitability.

Dependencies are inferred from the claim text.