Method and apparatus for optimizing electronic design
AssigneeMonterey Design Systems, Inc.
InventorsAra Markosian, Yaacov (Jacob) Greidinger, Siu-Tong Hui, Sedrak Sargisian
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Abstract
A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.
Claims40
A method for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge, said method for compacting comprising the steps of:
- forming paths extending from said bottom edge to said top edge, said paths intersecting cells of said initial layout;
- determining which of said paths are critical paths, each critical path contains line segments all of which are saturated;
- removing a set of said cells of said initial layout that are associated with said critical paths;
- replacing said set of said cells with replacement cells at one or more locations which allow said initial layout boundary to be reduced in a dimension;
- and
- reducing said initial layout boundary in said dimension.
An apparatus for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge, said apparatus comprising:
- means for forming paths extending from said bottom edge to said top edge, said paths intersecting cells of said initial layout;
- means for determining which of said paths are critical paths, each critical path containing line segments all of which are saturated;
- means for removing a set of said cells of said initial layout that are associated with said critical paths;
- means for replacing said set of said cells with replacement cells at one or more locations which allow said initial layout boundary to be reduced in a dimension;
- and
- means for reducing said initial layout boundary in said dimension.
A computer usable storage medium having computer readable program code embodied therein for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge said computer readable program code including:
- first computer readable program code, said first computer readable program code forms paths extending from said bottom edge to said top edge, said paths intersecting cells of said initial layout;
- second computer readable program code, said second computer readable program code determines which of said paths are critical paths, each critical path containing line segments all of which are saturated;
- third computer readable program code, said third computer readable program code removes a set of said cells of said initial layout that are associated with said critical paths;
- fourth computer readable program code, said fourth computer readable program code replaces said set of said cells with replacement cells at one or more locations which allow said initial layout boundary to be reduced in a dimension;
- and
- fifth computer readable program code, said fifth computer readable program code reduces said initial layout boundary in said dimension.
A method for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge, said method for compacting comprising the steps of:
- identifying one or more critical paths in said initial layout, said critical paths include adjacent cells which are too close together;
- identifying a first critical cut severing a set of said critical paths, said first critical cut identifies at least one cell from each critical path of said set of critical paths;
- and
- removing and replacing said at least one cell from each critical path.
One or more processor readable storage devices for storing processor readable code, said processor readable code for programming one or more processors to perform a method for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge, said method for compacting comprising the steps of:
- identifying one or more critical paths in said initial layout, said critical paths include adjacent cells which are too close together;
- identifying a first critical cut severing a set of said critical paths, said first critical cut identifies at least one cell from each critical path of said set of critical paths;
- and
- removing and replacing said at least one cell from each critical path.
An apparatus for compacting an initial electronic layout of cells within an initial layout boundary, said initial layout boundary including a bottom edge and a top edge, said apparatus comprising:
- an interface;
- a storage device;
- and
- a processor in communication with said interface and said storage device, said processor performs a method comprising the steps of:
- identifying one or more critical paths in said initial layout, said critical paths include adjacent cells which are too close together;
- identifying a first critical cut severing each of said critical paths, said first critical cut identifies at least one cell from each critical path;
- removing and replacing said at least one cell from each critical path;
- and
- reducing said initial layout boundary due to said step of removing and replacing.
Dependencies are inferred from the claim text.