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US 6,446,229 B1Granted
Method and apparatus for integrated flip-flop to support two test modes
AssigneeIntel Corporation
InventorsDale F. Merrick, Joachim Priesnitz
Life of this patent
Estimating the term…
Abstract
A circuit, an integrated flip flop, to receive an input in response to a clock signal. The integrated flip flop has a first and second slave latch and a master latch. The first slave latch receives an output from the master latch in response to the clock signal and a control signal for a first test mode of operation. The second slave latch receives an output from the master latch in response to the clock signal in one of a second test mode of operation or a normal functional mode of operation.
Claims16
A circuit comprising:
- a flip flop to receive an input in response to a clock signal, the flip flop comprising:
- a master latch to receive the input in response to the clock signal;
- a first slave latch to receive an output from the master latch in response to the clock signal and a control signal for a first test mode of operation;
- and
- a second slave latch to receive an output from the master latch in response to the clock signal in one of a second test mode of operation or a normal functional mode of operation.
2 more elements
A method comprising:
- receiving an input at a first latch in response to a clock signal;
- transmitting an output from the first latch to an input of a second latch in response to the clock signal and a control signal for a first test mode of operation;
- and
- transmitting an output from the first latch to an input of a third latch in response to the clock signal for a second test mode of operation.
1 more element
A circuit comprising:
- a master latch to receive an input in response to a clock signal;
- a first slave latch to receive an output from the master latch in response to the clock signal and a control signal for a first test mode of operation;
- and
- a second slave latch to receive an output from the master latch in response to the clock signal in either one of a second test mode of operation or a normal functional mode of operation.
1 more element
Dependencies are inferred from the claim text.