Semiconductor integrated circuit testing apparatus and method of controlling the same

An apparatus for testing a plurality of semiconductor integrated circuits, each including a memory portion and a logic portion, and having pins required for a memory test that tests the memory portion and pins required for a logic test using the memory and logic portions, said pins required for the memory test being included in the pins required for the logic test, said apparatus comprising:

• a semiconductor integrated circuit tester having at least one group of channels through which logic test signals required for the logic test are transmitted, said group of channels including sub-groups of channels, the number of which is equal to the number of the pins required for the memory test, and through which memory test signals required for the memory test are transmitted;
• IC sockets for fitting therein semiconductor integrated circuits to be tested, the number of which is determined depending on the number of semiconductor integrated circuits that can be simultaneously tested in the memory test;
• and
• a switching circuit connected between said IC sockets and said semiconductor integrated circuit tester;
• wherein
• each of said IC sockets has contacts coupled to the respective pins required for the logic test of the semiconductor integrated circuit under test fitted therein;
• and
• said switching circuit is switched between a first state and a second state in such a manner that,
• when said switching circuit is switched in the first state, respective sub-groups of channels are connected by said switching circuit to respective IC sockets such that the memory test signals required for the memory test are simultaneously supplied to contacts of the respective IC sockets coupled to the pins required for the memory test of the semiconductor integrated circuits, and
• when said switching circuit is switched in the second state, the group of channels is connected by said switching circuit to one of the IC sockets so that the logic test signals required for the logic test are supplied to the contacts of said one IC socket coupled to the pins required for the logic test of one semiconductor integrated circuit, and thereafter the group of channels is connected by said switching circuit to another of the IC sockets in sequence,
• whereby both the memory test and the logic test are performed by one testing apparatus.

A method of controlling a semiconductor integrated circuit testing apparatus, wherein the testing apparatus comprises:

• a semiconductor integrated circuit tester having a predetermined number of channels for supplying driving signals;
• IC sockets the number of which is the same as the number of memory portions of semiconductor integrated circuits that can be simultaneously tested by said tester, said number of IC sockets being determined depending on the number of the channels of said semiconductor integrated circuit tester and the number of the channels required for testing a memory portion of a semiconductor integrated circuit to be tested;
• and
• a switching circuit connected between said IC sockets and said semiconductor integrated circuit tester, said switching circuit switching between a state in which driving signals for testing memory portions of semiconductor integrated circuits under test are supplied to all of said IC sockets and a state in which driving signals for testing a logic portion or portions of a semiconductor integrated circuit or circuits under test are supplied to a part of said IC sockets;
• and wherein the method comprises:
• (a) simultaneously testing, at a time point when a testing for logic portions of the half of semiconductor integrated circuits under test among semiconductor integrated circuits under test mounted on said IC sockets has been completed, the memory portions of all of said semiconductor integrated circuits under test;
• (b) starting, at a time point when said testing for said memory portions has been completed, a testing for logic portions of the remaining half of the semiconductor integrated circuits under test among said semiconductor integrated circuits under test;
• (c) first exchanging, during the testing for the logic portions of the remaining half of the semiconductor integrated circuits under test, the first half of the semiconductor integrated circuits whose logic portions and memory portions have been tested for semiconductor integrated circuits to be tested next;
• (d) starting a testing for the logic portions of the exchanged semiconductor integrated circuits under test at a time point when the testing for the logic portions of said remaining half of the semiconductor integrated circuits under test has been completed, and secondly exchanging, during the testing for the logic portions of the exchanged semiconductor integrated circuits under test, said remaining half of the semiconductor integrated circuits under test whose logic portions and memory portions have been tested for semiconductor integrated circuits to be tested next;
• and
• (e) simultaneously testing, after said secondly exchanging step, at a time point when the testing for the logic portions of the semiconductor integrated circuits under test exchanged in said first exchanging step has been completed, the memory portions of all of the semiconductor integrated circuits under test exchanged in said first and second exchanging steps;
• whereby semiconductor integrated circuits can be tested substantially with no idle time by repeating said steps (b) to (e).