Semiconductor memory device
AssigneeNEC Corporation
InventorHiroaki Hashimoto
Life of this patent
Estimating the term…
Abstract
The semiconductor memory device of the present invention is characterized in the provision of: data amps provided to each output terminal for amplifying the voltage of data read out from a memory cell, outputting the result as a first output data, and outputting a second output data which is generated from this first output data; a data compressing circuit for compressing the first output data from each the output terminal, and performing testing to determine whether or not this first output data read out from the memory cell is normal based on the compressed results; a plurality of first lines for outputting each the first output data to the data compressing circuit from the data amps; and a second line for connecting and outputting the second output data from the data amps to the data compressing circuit using a wired OR.
Claims9
A semiconductor memory device comprising:
- data amps provided to each output terminal for amplifying the voltage of data read out from a memory cell, outputting the result as a first output data, and outputting a second output data which is generated from this first output data;
- a data compressing circuit for compressing said first output data from each said output terminal, and performing testing to determine whether or not this first output data read out from the memory cell is normal based on the compressed results;
- a plurality of first lines for outputting each said first output data to said data compressing circuit from said data amps;
- and
- a second line for connecting and outputting said second output data from said data amps to said data compressing circuit using a wired OR.
A semiconductor memory device, comprising:
- data amps provided to each output terminal for amplifying the voltage of the data read out from a memory cell, outputting the result as a first output data, and outputting a second output data generated from this first output data;
- a data compressing circuit for compressing said first output data of each said output terminal, and performing testing to determine whether or not this first output data read out from the memory cell is normal based on the results of this compression;
- a plurality of first lines for outputting each said first output data to said data compressing circuits from these data amps;
- and
- a second line for connecting a plurality of OR circuits for performing an OR operation between said second output data output from said data amps and the second data output from other adjacent data amps;
- performing an OR operation between the result of the preceding OR operation and the second output data output from other next adjacent data amps;
- performing an OR operation on the second data of all the data amps sequentially;
- and outputting the result of this operation to said data compressing circuit as third output data.
Dependencies are inferred from the claim text.