Debug mechanism for data processing systems

Apparatus for processing data, said apparatus comprising:

• a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations;
• and
• a coprocessor coupled to said main processor via a coprocessor interface and responsive to coprocessor instructions within said stream of instructions to perform coprocessor operations;
• wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor, wherein said debug coprocessor comprises one or more debug coprocessor registers, wherein said main processor comprises an instruction address bus for transmitting instruction addresses associated with instructions within said stream of instructions, said one or more debug coprocessor registers includes a breakpoint register for storing a breakpoint value and said debug coprocessor includes a breakpoint comparator for comparing said breakpoint value with said instruction addresses upon said instruction address bus and generating a breakpoint indication signal when said breakpoint value matches an instruction address upon said instruction address bus.

Apparatus for processing data, said apparatus comprising:

• a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations;
• and
• a coprocessor coupled to said main processor via a coprocessor interface and responsive to coprocessor instructions within said stream of instructions to perform coprocessor operations;
• wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor, wherein said debug coprocessor comprises one or more debug coprocessor registers, wherein said main processor comprises an data address bus for transmitting data addresses associated with data values processed by said apparatus for processing data, said one or more debug coprocessor registers includes a watchpoint register for storing a watchpoint value and said debug coprocessor includes a watchpoint comparator for comparing said watchpoint value with said data addresses upon said data address bus and generating a watchpoint indication signal when said watchpoint value matches an data address upon said data address bus.

Apparatus for processing data, said apparatus comprising:

• a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations;
• and
• a coprocessor coupled to said main processor via a coprocessor interface and responsive to coprocessor instructions within said stream of instructions to perform coprocessor operations;
• wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor, wherein said debug coprocessor comprises one or more debug coprocessor registers, wherein at least one of said one or more debug coprocessor registers is accessed via a serial scan chain, said serial scan chain operating under control of a scan chain controller.

Apparatus for processing data, said apparatus comprising:

• a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations;
• and
• a coprocessor coupled to said main processor via a coprocessor interface and responsive to coprocessor instructions within said stream of instructions to perform coprocessor operations;
• wherein said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor, wherein said coprocessor interface includes one or more signal lines for transferring signals generated by said debug coprocessor during debugging operation including one or more of:
• a signal to trigger a hold in a main processor pipeline of said main processor;
• a signal to trigger a hold in a coprocessor pipeline of a further coprocessor coupled to said coprocessor bus;
• and a signal to trigger cancelling of a coprocessor operation in said further coprocessor.

A method of processing data in a data processing apparatus, said method comprising the steps of:

• in response to main processor instructions within a stream of instructions input to a main processor, performing main processor operations;
• in response to coprocessor instructions within said stream of instructions, controlling a coprocessor coupled to said main processor via a coprocessor interface to perform coprocessor operations;
• wherein
• said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging at least one portion of said apparatus external of and connected to said coprocessor, and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor.