Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications
AssigneeInternational Business Machines Corporation
InventorAlbert Alfonse Slane
Life of this patent
Estimating the term…
Abstract
A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of instruction is evaluated. Responsive to the one-of instruction control, a next instruction pointer is generated. A one-of-and-jump instruction is evaluated. Responsive to the one-of-and-jump instruction control, a first next instruction pointer and a second next instruction pointer are generated. The second next instruction pointer is a destination instruction pointer for the one-of-and-jump instruction.
Claims9
A method for processing data communications in a communications system using a small processor including an arithmetic logic unit (ALU) and an instruction memory, said method comprising the steps of:
- evaluating a one-of instruction control;
- responsive to a false one-of instruction control, updating an instruction pointer to a first instruction pointer;
- responsive to a true one-of instruction control, updating an instruction pointer to a second instruction pointer;
- and
- evaluating a one-of-and-jump instruction control.
Apparatus for processing data communications in a communications system comprising:
- an arithmetic logic unit (ALU);
- an instruction pointer (IP) register;
- an instruction memory coupled to said arithmetic logic unit (ALU);
- said instruction memory applying a current instruction to said ALU responsive to an instruction pointer (IP) coupled from said instruction pointer (IP) register;
- and
- a next instruction pointer (IP) generation logic coupled to said arithmetic logic unit (ALU) receiving a jump result control;
- said next instruction pointer (IP) generation logic generating a next instruction pointer (IP);
- said next instruction pointer (IP) generation logic including a first multiplexer receiving a one-of instruction control;
- said first multiplexer receiving a true input and a false input and providing a selected output responsive to said one-of-instruction control;
- an adder providing a result;
- said adder having a first input receiving a selected output of said first multiplexer and having a second input receiving a current instruction pointer;
- and said adder result corresponding to said next instruction pointer (IP) coupled to said instruction pointer register.
A computer program product for use with an embedded processor for processing receive and transmit data communications in a communications system, the computer program product comprising:
- a recording medium;
- a one-of instruction, recorded on said recording medium, for providing a next instruction pointer, and
- a one-of-and-jump instruction, recorded on said recording medium, for providing a next instruction pointer and a next next jump destination instruction pointer.
Dependencies are inferred from the claim text.