Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register

A method for efficient wrap detection in a microprocessor system, the system microprocessor including a plurality of rename buffers, the method comprising:

• providing at least one virtual rename buffer for allocation when one of a plurality of physical rename buffers is unavailable;
• allocating a virtual rename buffer to a target of an instruction;
• providing a one or more virtual bit for each of the plurality of physical rename buffers to identify to which of the at least one virtual rename buffer each of the plurality of physical rename buffers is currently mapped;
• providing a means for identifying a one of the plurality of physical rename buffers that has currently become available;
• identifying whether a virtual rename buffer of the at least one virtual rename buffer allocated to a particular instruction is currently associated with one of the plurality of physical rename buffers by comparing the one or more virtual bit of a predetermined one or the plurality of physical rename buffers, an identification of a one of the plurality of physical rename buffers that has currently become available, and an identification of the virtual rename buffer.

A system for efficient wrap detection, the system comprising:

• a plurality of rename buffers, at least one of which is a virtual rename buffer;
• a target buffer pointer that points to a one of the at least one virtual rename buffer allocated to a target;
• a completion pointer that points to the next physical rename buffer position to become available as instructions complete;
• a flag associated with one of a plurality of physical rename buffers that indicates the at least one virtual rename buffer with which the one of a plurality of physical rename buffers is currently associated;
• a logic unit for comparing the target buffer pointer, the completion pointer, and the flag to determine whether an instruction may issue.

An apparatus in a microprocessor system, the microprocessor system including a plurality of rename buffers, the apparatus comprising:

• first performing means for performing a two's complement subtraction of a completion pointer from a target pointer, the target pointer pointing to a rename buffer allocated to an instruction and the completion buffer pointing to a next buffer position to free as instructions are completed, wherein a carry out results from the two's complement subtraction;
• exclusive OR means for performing an exclusive OR operation using the carry out and a virtual bit associated with a highest rename buffer within the plurality of rename buffers to form a result, wherein the virtual bit is used to map a physical buffer onto a virtual buffer;
• comparing means for comparing the result with a most significant bit of the target pointer;
• and
• indicating means, responsive to a match between the a most significant bit of the target pointer and the result, for indicating that an instruction can be issued.