Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture
AssigneeAgere Systems Guardian Corp.
InventorsMazhar M. Alidina, Sivanand Simanapalli, Larry R. Tate
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Abstract
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and apparatus enable vectoring the respective first and second high parts from the accumulators to define a single vectored register responsive to a single instruction cycle and processing the data in the vectored register.
Claims24
A method for reducing cycles utilized in a digital signal processor, said processor including a multiplier unit, an adder, a memory and a plurality of accumulators, each including a high and low part, said method comprising the steps of:
- associating data of a first accumulator with data of a second accumulator to define a single vectored data structure;
- and
- transferring said vectored data structure between portions of said digital processor that store data in the manner of single register, whereby the first and second accumulator data comprising said vectored data structure are processed concurrently in a single operation.
A vectored register for use in a digital signal processor comprising a plurality of accumulators, a multiplier unit, an adder, and a memory, said accumulators including respective high and low parts, said vectored register comprising:
- a first part from a first of said accumulators;
- and
- a second part from a second of said accumulators, said first and second parts being associated with each other in order to define a single vectored data structure for transferring between portions of said digital processor that store data in the manner of a single register, thereby effecting more rapid data processing.
In a digital signal processor comprising a plurality of accumulators, a multiplier unit, and a memory, said accumulators including respective high and low parts, a vectored register comprising:
- a first part from a first accumulator;
- and
- a second part from a second accumulator, said first and second parts defining a vector to effect storing to said memory in a single instruction cycle.
A register array for use in a digital signal processor employing a dual Multiply-Accumulate architecture, said register array including:
- a plurality of accumulators, said accumulators including respective high and low parts, said a pair of parts from different accumulators together defining a vector;
- a multiplier unit disposed in data communication with said plurality of accumulators to selectively receive data loaded from said defined vector;
- and
- a memory connected to said plurality of accumulators to alternatively store data loaded from or load data to said defined vector whereby said vector is responsive to a single instruction cycle to effect said loading or storing operations.
A reduced instruction data arithmetic unit for use in a digital signal processor, said unit including:
- a data computation module for calculating values from respective sets of data and including a multiplier unit;
- and
- a data transfer path for directing the output of said calculated values and comprising a plurality of bus-accessible data path registers including
- respective output product registers, and
- a register array including a plurality of accumulators, said accumulators including respective high and low parts, the parts of different registers cooperatively defining a vector, said multiplier unit disposed downstream of said plurality of accumulators to receive data loaded from said defined vector, and a memory connected to said plurality of accumulators to store data from and load data to said defined vector, whereby said vector is effective to perform said loading or storing operations in a single instruction cycle.
Dependencies are inferred from the claim text.