US 6,446,189 B1Granted

Computer system including a novel address translation mechanism

AssigneeAdvanced Micro Devices, Inc.

InventorsGerald D. Zuraski, Jr., Frederick D. Weber, William A. Hughes, William K. Lewchuk, Scott A. White, Michael T. Clark

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Abstract

A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.

Claims24

Dependent claims

A processor, comprising:

a cache unit for storing data items, wherein said cache unit is coupled to receive a linear address and comprises a translation lookaside buffer (TLB) for storing a plurality of linear addresses and corresponding physical addresses, and wherein said cache unit is configured to provide said linear address when a physical address corresponding to said linear address is not found within said TLB;
a bus interface unit coupled to receive said linear address from said cache unit and configured to provide a physical address corresponding to said linear address to said cache unit;
wherein said linear address comprises a first plurality of address signals, and wherein the bus interface unit comprises:
address translation circuitry coupled to receive said first plurality of address signals, and wherein said address translation circuitry is configured to produce a second plurality of address signals from said first plurality of address signals;
a multiplexer coupled to receive said first and second plurality of address signals and a paging signal, wherein said multiplexer is configured to produce a third plurality of address signals, and wherein said third plurality of address signals is either said first plurality of address signals or said second plurality of address signals dependent upon said paging signal;
and
gating logic coupled to receive at least one of said third plurality of address signals and a first masking signal, and wherein said gating logic is configured to either pass the at least one of said third plurality of address signals or to mask the at least one of said third plurality of address signals dependent upon said first masking signal;
and
wherein said bus interface unit provides the third plurality of address signals acted upon by said gating logic to said cache unit as the physical address corresponding to said linear address.

6 more elements

Dependencies are inferred from the claim text.