Loading patent…
AssigneeHewlett-Packard Company
InventorsReid James Riedlinger, Samuel D Naffziger, Douglas J Cutter, Christopher Craig Seib
Estimating the term…
A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a page mask along with the physical page numbers, and includes local multiplexers which perform virtual address bypassing of the physical page number when the page has been masked.
A translation lookaside buffer (TLB) for a cache, the cache receiving a virtual address comprising a virtual page number and a virtual index and translating the virtual address to a physical address of a page stored in said cache if the page is present in the cache, the TLB comprising:
A method of accessing data in a cache, the method comprising the following steps:
A translation lookaside buffer (TLB) for a cache, the cache receiving a virtual address comprising a virtual page number and a virtual index and translating the virtual address to a physical address of a page stored in said cache if the page is present in the cache, the TLB comprising:
Dependencies are inferred from the claim text.