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US 6,446,181 B1Granted
System having a configurable cache/SRAM memory
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsHebbalalu S. Ramagopal, David B. Witt, Michael Allen, Moinul Syed, Ravi Kolagotla, Lawrence A. Booth, Jr., William C. Anderson
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Abstract
An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.
Claims19
A system comprising:
- a core processor having n number of ports;
- and
- a plurality of memory banks coupled to at least one port, said plurality of memory banks being connected in such a way as to provide substantially simultaneous data accesses for said core processor,
- wherein a number of said plurality of memory banks is greater than said n number of ports in the core processor, and
- wherein each of a plurality of said memory banks is user-confiurable as an SRAM or a cache.
2 more elements
A system comprising:
- a core processor including
- n number of ports,
- a program sequencer,
- first and second data address generators coupled to said program sequencer, where said first and second data address generators provide addresses for said data accesses, and
- a store buffer to store result of a computation;
- a plurality of memory banks coupled to said at least one port, where said plurality of memory banks are connected in such a way as to provide substantially simultaneous data accesses for said core processor, and where a number of said plurality of memory banks is greater than said n number of ports in the core processor;
- a first memory bus coupled to said first data address generator and said plurality of memory banks;
- a second memory bus coupled to said second data address generator and said plurality of memory banks;
- and
- a third memory bus coupled to said buffer and said plurality of memory banks.
7 more elements
An apparatus comprising:
- a digital signal processor core having a data port;
- and
- a memory system having a plurality of blocks coupled to said data port, where said plurality of blocks are connected in such a way as to provide substantially simultaneous data accesses through said data port to said digital signal processor core, and where each of a plurality of said blocks is configurable as an SRAM or a cache.
An apparatus comprising:
- a digital signal processor core having a data port;
- a memory system having a plurality of blocks coupled to said data port, where said plurality of blocks are connected in such a way as to provide substantially simultaneous data accesses through said data port to said digital signal processor core;
- a plurality of memory busses to transport data to/from said data port from/to said plurality of blocks;
- and
- a plurality of multiplexers to selectively connect said plurality of blocks to said plurality of memory busses.
2 more elements
An apparatus comprising:
- a core processor having at least one data port;
- and
- a memory system connected in such a way as to provide substantially simultaneous data accesses through said at least one data port, where said memory system includes a plurality of memory banks, each memory bank adapted to be user configurable as either an SRAM or a cache.
Dependencies are inferred from the claim text.