Computer system with dram bus

A computer system comprising:

• a processor;
• a memory system, which includes:
• DRAM devices;
• a memory controller hub (MCH) to control access to the DRAM devices, the MCH having a first channel for communicating with the DRAM devices according to a first protocol;
• a memory repeater hub (MRH) of a first type having an input connected to the first channel of the MCH and providing second and third channels as outputs, the second and third channels operating in accordance with the first protocol;
• a first pair of MRHs of a second type, each having an input connected to the second channel and each providing a pair of DRAM channels that operate in accordance with a second protocol;
• a second pair of MRHs of the second type, each having an input connected to the third channel and each providing a pair of DRAM channels that operate in accordance with the second protocol.

A computer system comprising:

• a processor;
• a memory system, which includes:
• DRAM devices;
• a memory controller hub (MCH) to control access to the DRAM devices, the MCH having a first channel for communicating with the DRAM devices according to a first protocol;
• a first memory repeater hub (MRH) of a first type having an input connected to the first channel of the MCH and providing second and third channels as outputs, the second and third channels operating in accordance with the first protocol;
• a second memory repeater hub (MRH) of the first type having an input connected to the first channel of the MCH and also providing the second and third channels as outputs;
• a first pair of MRHs of a second type, each having an input connected to the second channel of the first MRH and each providing a pair of DRAM channels that operate in accordance with a second protocol;
• a second pair of MRHs of the second type, each having an input connected to the third channel of the first MRH and each providing a pair of DRAM channels that operate in accordance with the second protocol;
• a third pair of MRHs of a second type, each having an input connected to the second channel of the second MRH and each providing a pair of DRAM channels that operate in accordance with a second protocol;
• a second pair of MRHs of the second type, each having an input connected to the third channel of the second MRH and each providing a pair of DRAM channels that operate in accordance with the second protocol.