Method and system for controlling the memory access operation performed by a central processing unit in a computer system

A memory access control system for controlling a memory access operation by a central processing unit (CPU) to a memory unit, wherein the CPU can access desired data on the memory unit through the memory access control system, the system comprising:

• a CPU interface coupled to the CPU for receiving a CPU read request and issuing a corresponding internal access request after the CPU read request being received by a latency, but before a checking time point that is for determining whether or not a level 1 (L1) cache write-back signal is issued later, wherein if the CPU later issues the level 1 (L1) cache write-back signal corresponding to the read request signal at the checking time point, then the CPU interface issues a read-stop signal when the last data block of the read request is received;
• and
• a memory control unit, coupled between the CPU interface and the memory unit, in which the memory control unit can access the desired data according to the internal access request, wherein as the memory control unit receives the read-stop signal, the memory control unit disregards received internal access requested data and immediately starts to write the write-back-data, issued by the CPU, into the memory unit.