SRAM with tag and data arrays for private external microprocessor bus

A computer system, comprising:

• a cache memory including a cache data portion and a tag data portion, the cache data portion having an address bus port, a cache data bus port, and a cache control bus port, and the tag data portion having a tag data bus port and a tag control bus port;
• a processor having an address bus port, a cache data bus port, a cache control bus port, a tag data bus port, and a tag control bus port, the processor outputting to the cache data portion a write cancel instruction to cancel a cache write command after write data from the processor have been coupled to the cache data portion responsive to a cache write miss;
• an address bus coupled to the address bus port of the processor and to the address bus port of the cache data portion of the cache memory;
• a cache data bus coupled to the cache data bus port of the processor and to the cache data bus port of the cache data portion of the cache memory;
• a cache control bus coupled to the cache control bus port of the processor and to the cache control bus port of the cache data portion of the cache memory;
• a tag data bus coupled to the tag data bus port of the processor and to the tag data bus port of the tag data portion of the cache memory;
• and
• tag control bus coupled to the tag control bus port of the processor and to the tag control bus port of the tag data portion of the cache memory.

A computer system comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and allowing data to be entered into the computer system;
• an output device coupled to the processor through the processor bus allowing data to be output from the computer system;
• a system memory coupled to the processor through the processor bus, the system memory;
• and
• a cache memory system comprising:
• a private bus coupled to the processor for exchanging tag data and cache data with a cache memory system;
• a cache memory and a tag memory coupled to the private bus;
• means coupled to the processor for snooping the cache memory system during a burst transfer of data from the processor to the cache memory system in a cache write operation, the snooping means operating during the burst transfer of write data without interrupting the burst transfer of write data;
• and
• means for providing a write cancel instruction to the cache memory for canceling a cache write command after the write data from the processor have been coupled from the processor to the cache memory.

In a computer system, a method of snooping a cache memory system capable of storing tag data and cache data, and transferring cache data in a burst transfer mode, the method comprising:

• addressing the cache memory to transfer cache data to or from the cache memory during a burst cache data transfer;
• transferring a burst of cache data to the cache memory;
• addressing the cache memory to transfer tag data from the cache memory;
• while the burst of cache data is being transferred from the cache memory, transferring tag data to or from the cache memory;
• detecting from the tag data transferred from the cache memory whether there is a cache miss condition;
• and
• canceling the writing of the burst of cache data to the cache memory in the event the cache miss condition is detected.

A method for processing a cache write miss comprising:

• sending a first address from a processor to a cache memory;
• sending a first tag read request from the processor to a tag memory associated with the cache memory;
• sending a cache write request to write cache data to the first address in the cache memory;
• reading first tag data from the first address in the tag memory;
• determining in the processor that the cache write request is a cache miss from the first tag data;
• and
• sending a write cancel instruction to the cache memory to inhibit writing the write data to the first address.

A computer system, comprising:

• a cache memory;
• a processor having a system bus port and a private bus port;
• the processor performing snoops of the cache memory during a write of cache data from the processor to the cache memory, the processor further canceling the writing of cache data to the cache memory responsive to the snoop of the cache memory indicating a cache write miss;
• a system bus coupled to the system bus port of the processor;
• a private bus coupled to the private bus port of the processor and to the cache memory;
• and
• a system memory coupled to the system bus.

A computer system, comprising:

• a processor having a system bus port and a private bus port;
• a cache memory having a cache data portion and a tag data portion, the cache data portion comprising:
• an address register storing an address applied to the cache data portion and outputting from the address register an internal address;
• a burst counter coupled to an output of the address register, the burst counter incrementing the internal address responsive to a clock signal;
• a data input register coupled to receive and store cache data from the processor;
• a memory array having an address input coupled to the address register and the burst counter, a data input coupled to an output of the data input register, and a data output, the memory array storing data applied to its data input at a location in the memory array indicated by the internal address, the memory array further outputting data to its data output from a location in the memory array indicated by the internal address;
• a data output register coupled to the data output of the memory array to apply cache data to the processor;
• and
• a write cancel register canceling writing of data to the cache data portion responsive to a write cancel command, and wherein the processor is structured to generate the write cancel command responsive to reading tag data from the tag data portion indicative of a cache write miss;
• a system bus coupled to the system bus port of the processor;
• a private bus coupled to the private bus port of the processor and to the cache memory;
• and
• a system memory coupled to the system bus.

A computer system, comprising:

• a processor having an address bus port, a cache data bus port, a cache control bus port, a tag data bus port, and a tag control bus port;
• an address bus coupled to the address bus port of the processor;
• a cache data bus coupled to the cache data bus port of the processor;
• a cache control bus coupled to the cache control bus port of the processor;
• a tag data bus coupled to the tag data bus port of the processor;
• tag control bus coupled to the tag control bus port of the processor;
• and
• a cache memory including a cache data portion and a tag data portion, the cache data portion having an address bus port coupled to the address bus, a cache data bus port coupled to the cache data bus, and a cache control bus port coupled to the cache control bus, and the tag data portion having a tag data bus port coupled to the tag data bus and tag control bus port coupled to the tag control bus, the cache data portion comprising:
• an address register coupled to the address bus, the address register storing an address applied to the address bus and outputting from the address register an internal address;
• a burst counter coupled to an output of the address register, the burst counter incrementing the internal address responsive to a clock signal;
• a data input register coupled to the cache data bus, the data input register receiving and storing cache data applied to the cache data bus;
• a memory array having an address input coupled to the address register and the burst counter, a data input coupled to an output of the data input register, and a data output, the memory array storing data applied to its data input at a location in the memory array indicated by the internal address, and outputting data to its data output from a location in the memory array indicated by the internal address;
• a data output register coupled to the data output of the memory array, the data output register applying cache data to the cache data bus;
• and
• a write cancel register canceling writing of data to the cache data portion responsive to a write cancel command, and wherein the processor generates the write cancel command responsive to reading tag data from the tag data portion indicative of a cache write miss.

A computer system comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• a system memory coupled to the processor through the processor bus, the system memory;
• and
• a cache memory system comprising:
• a private bus coupled to the processor for exchanging tag data and cache data with a cache memory system;
• and
• a cache memory and a tag memory coupled to the private bus;
• means coupled to the processor for snooping the cache memory system during a cache memory read operation to determine when data from the cache memory are stale;
• and
• means for ignoring stale cache memory data when the snooping means determines that the cache memory data are stale.