Cache prefetching of L2 and L3
AssigneeInternational Business Machines Corporation
InventorsMichael John Mayfield, Francis Patrick O'Connell, David Scott Ray
Life of this patent
Estimating the term…
Abstract
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.
Claims18
A method for prefetching comprising the steps of:
- sending a prefetch request to a second level cache, wherein the prefetch request includes a signal for notifying a third level cache coupled to the second level cache that the third level cache should prefetch also;
- prefetching data into the second level cache in response to the prefetch request;
- and
- prefetching data into the third level cache in response to the prefetch request.
A data processing system comprising:
- a processor including a load/store unit having an L1 cache;
- a prefetch engine for monitoring load misses in the load/store unit;
- an L2 cache;
- an L3 cache;
- a bus system for transferring data between the L1 cache, L2 cache, and L3 cache and the load misses from the L1 cache to the prefetch engine;
- and
- a private prefetch request bus for transmitting a prefetch request from the prefetch engine to the L2 and L3 caches, wherein the private prefetch request bus is separate from the bus system, wherein the prefetch request includes a signal for notifying the L3 cache that the L3 cache should prefetch.
A multiprocessor system comprising:
- a first processor including a first L1 cache and a first prefetch engine;
- a second processor including a second L1 cache and a second prefetch engine;
- an L2 cache shared by the first and second processors;
- a fabric coupled to the L2 cache and adaptable for coupling to a third processor;
- an L3 cache;
- system memory coupled to the L3 cache;
- a first bus system for transferring data between the first L1 cache, L2 cache, and L3 cache and load misses from the first L1 cache to the first prefetch engine;
- a second bus system for transferring data between the second L1 cache, L2 cache, and L3 cache and load misses from the second L1 cache to the second prefetch engine;
- a first private prefetch request bus for transmitting prefetch requests from the first prefetch engine to the L2 and L3 caches, wherein the first private prefetch request bus is separate from the first bus system;
- and
- a second private prefetch request bus for transmitting prefetch requests from the second prefetch engine to the L2 and L3 caches, wherein the second private prefetch request bus is separate from the second bus system, wherein the prefetch requests include a signal for notifying the L3 cache that the L3 cache should prefetch.
Dependencies are inferred from the claim text.