Address dependent caching behavior within a data processing system having HSA (hashed storage architecture)
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Leo James Clark, John Steve Dodson, Guy Lynn Guthrie, Jerry Don Lewis
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Abstract
A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
Claims23
A processor, comprising:
- at least one execution unit;
- an instruction sequencing unit coupled to said at least one execution unit;
- and
- a plurality of caches at a same level that store data utilized by said at least one execution unit, wherein each cache among said plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space, and wherein said plurality of caches have diverse caching behaviors, such that at least two of said plurality of caches at said same level concurrently implement at least one of different (1) store-through/write-back policies (2) cache line replacement policies (3) coherence protocols or (4) prefetch behaviors.
A data processing system, comprising:
- at least one system interconnect;
- at least one system memory coupled to said at least one system interconnect;
- and
- at least one processor coupled to said system interconnect, wherein each processor includes:
- at least one execution unit;
- an instruction sequencing unit coupled to said at least one execution unit;
- and
- a plurality of caches at a same level that store data utilized by said at least one execution unit, wherein each cache among said plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space, and wherein said plurality of caches have diverse caching behaviors, such that at least two of said plurality of caches at said same level concurrently implement at least one of different (1) store-through/write-back policies (2) cache line replacement policies (3) coherence protocols or (4) prefetch behaviors.
A method within a processor for caching data, wherein said a processor includes a plurality of caches at a same level that store data utilized by said processor, said method comprising:
- storing within a first cache among said plurality of caches only data having associated addresses within a first subset among a plurality of subsets of an address space;
- and
- storing within a second cache among said plurality of caches only data having associated addresses within a second subset among a plurality of subsets of an address space;
- and
- implementing diverse caching behaviors in said first and second caches, such that at least two of said plurality of caches at said same level concurrently implement at least one of different (1) store-through/write-back policies (2) cache line replacement policies (3) coherence protocols or (4) prefetch behaviors.
Dependencies are inferred from the claim text.