Test mode accessing of an internal cache memory

A method for writing an internal cache memory of an integrated circuit during a test mode, said integrated circuit including a central processing unit and coupled to an external memory and an external bus, said external bus having a portion that is shared by data signals and address signals over a bus cycle of two or more clock periods, said memory comprising the steps of:

• providing within said integrated circuit an internal bus interfaced to said internal cache memory;
• providing within said integrated circuit a read buffer and a write buffer for storing data received from said external memory and data to be stored into said external memory, respectively, said read buffer and said write buffer being coupled to said internal bus and said plurality of terminals during a functional operation not under said test mode;
• and
• in response to receiving a command indicating said test mode,
• (a) stalling said central processing unit and decoupling said read buffer and said write buffer from said internal bus and said plurality of terminals;
• (b) receiving into said integrated circuit, from said external bus, a logic signal indicating a write access to said internal cache memory and said address signals specifying a location in said internal cache memory;
• and
• (c) transferring said data signals from said external bus to said internal bus and writing said data signals into said location of said internal cache memory during said write access of said internal cache memory.

A method for reading an internal cache memory of an integrated circuit, said integrated circuit including a central processing unit and coupled to an external memory and an external bus, said external having a portion that is shared by address signals and data signals over a bus cycle of two or more clock periods, said method comprising the steps of:

• providing within said integrated circuit an internal bus interfaced to said internal cache memory;
• providing within said integrated circuit a read buffer and a write buffer for storing data received from said external memory and data to be stored into said external memory, respectively, said read buffer and said write buffer being coupled to said internal bus and said plurality of terminals during a functional operation not under said test mode;
• and
• in response to receiving a command indicating said test mode, (a) stalling said central processing unit and decoupling said read buffer and said write buffer from said internal bus and said plurality of terminals;
• (b) receiving into said integrated circuit, from said external bus, a logic signal indicating a read access of said internal cache memory and address signals specifying a location in said internal cache memory;
• and
• (c) reading, during said read access of said internal cache memory, stored data from said location of said internal cache memory, providing said stored data on said internal bus, and transferring said stored data as said data signals on said external bus.