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AssigneeInternational Business Machines Corporation
InventorsBruce G. Hazelzet, Christopher P. Miller, Clarence R. Ogilvie, Paul C. Stabler
Estimating the term…
A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and the locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also “snoop” the memory bus when it is unavailable to the control of the DSP, i.e. when the system has control of the memory bus. The memory bus controller passes addresses and data to the DSP as it is received. When the DSP receives addresses that are in its normal or regular range, or other selected ranges, for processing in the memory. The DSP can capture the data and do “early” processing or pre-processing of this information before the DSP gains control of the memory.
A memory module for a computer system having a CPU comprising:
A computer system comprising a CPU, including a memory sub-system, said memory sub-system comprising:
A method of operating a memory sub-system connected to a CPU of a computer system, and wherein said memory sub-system has memory chips on a memory card, a memory bus selectively connectable to the CPU and controlled by a memory bus control element, and a signal processing element, connected to said memory bus control element, comprise the steps of:
A method of operating a memory sub-system connected to a CPU of a computer system, and wherein said memory sub-system has memory chips, a memory bus selectively connectable to the CPU and controlled by a memory bus control element, and a signal processing element, connected to said memory bus control element, comprising the steps of:
A method of operate a memory sub-system connected to a CPU of a computer system, and wherein said memory sub-system has memory chips, a memory bus selectively connectable to the CPU and controlled by a memory bus control element, and a signal processing element, connected to said memory bus control element, comprising the steps of:
A method of operating a memory sub-system connected to a CPU of a computer system, and wherein said memory sub-system has memory chips, a memory bus selectively connectable to the CPU and controlled by a memory bus control element, and a signal processing element, connected to said memory bus control element, comprising the steps of:
A method of operating a memory sub-system connected to a CPU of a computer system, and wherein said memory sub-system has memory chips, a memory bus selectively connectable to the CPU and controlled by a memory bus control element, and a signal processing element, connected to said memory bus control element, comprising the steps of:
Dependencies are inferred from the claim text.