Semiconductor circuit and method of controlling the same

A method of controlling a semiconductor circuit including a DRAM comprising the steps of:

• writing data, having time periods from being written in to being read out, on a common row of said DRAM based on at least one of overlapping and proximity of the time periods to each other;
• and
• refreshing said common row only during the time period from the first writing in of the data to the last reading out thereof.

A method of controlling a semiconductor circuit including a DRAM comprising the steps of:

• obtaining a memory capacity required by an application using said DRAM and writing, in turn, data in said DRAM in an order from a longer data retention time row to a shorter data retention time row with reference to a table having previously obtained data retention time of each row of said DRAM;
• and
• setting a refreshing cycle time on the basis of a row having the shortest data retention time of the rows to which data is stored to reduce the refreshing cycle time.

A semiconductor circuit including a DRAM characterized by comprising:

• a unit for writing data so that a number of rows of the DRAM storing data thereon is reduced;
• and
• a selective refreshing unit for selectively refreshing said rows based on storage of the data thereon, whereby rows absent data are not refreshed.

A semiconductor circuit including a DRAM comprising:

• a unit for writing data, having time periods from being written in to being read out on a common row of said DRAM based on at least one of overlapping and proximity of the time periods to each other;
• and
• a refreshing unit for refreshing said common row only during the time period from the first writing in of the data to the last reading out thereof.

A semiconductor circuit including a DRAM comprising:

• a unit for obtaining a memory capacity required by an application using said DRAM and writing, in turn, data in said DRAM in an order from a longer data retention time row to a shorter data retention time row with reference to a table having the previously obtained data retention time of each row of said DRAM;
• and
• a unit for setting a refreshing cycle time on the basis of a row having the shortest data retention time of the rows to which data is stored to reduce the refreshing cycle time.