Self-modifying synchronization memory address space and protocol for communication between multiple busmasters of a computer system

A synchronization method permitting shared memory communication between multiple busmasters in a computer system using semaphore memory cells of a synchronization memory address space, each semaphore memory cell having an idle state or a busy state, comprising the steps of:

• reading state information in a semaphore memory cell by a busmaster, the semaphore memory cell being coupled between a host bus of the computer system and the busmaster, the self-modifying synchronization memory address space being accessible by the plurality of busmasters independent of the host bus;
• self-switching of the semaphore memory cell to a busy state responsive to said read to the semaphore memory cell if the state information read by the busmaster corresponds to an idle state so that the busmaster owns the semaphore memory cell;
• and
• retaining the busy state of the semaphore memory cell until a subsequent action by the busmaster that owns the semaphore memory cell triggers the semaphore memory cell to switch itself to the idle state,
• wherein the step of reading state information is performed repeatedly by the busmaster until the semaphore memory cell is in the idle state.

A computer system adapted for a self-modifying synchronization memory protocol for multiple busmasters, comprising:

• at least one processor;
• at least one host bus coupled to the host processor;
• a plurality of busmasters;
• a self-modifying synchronization memory address space coupled to the host bus and including at least one semaphore memory cell having an idle state or a busy state, the self-modifying synchronization memory address space being coupled between the host bus and the plurality of busmasters, the self-modifying synchronization memory address space being accessible by the plurality of busmasters independent of the host bus;
• the semaphore memory cell switching itself to a busy state only if the semaphore memory cell is read by a busmaster of the plurality of busmasters when the semaphore memory cell is in an idle state so that the semaphore memory cell is owned by the busmaster;
• and
• a shared critical resource mapped into the self-modifying synchronization memory address space,
• wherein the semaphore memory cell retains the busy state until a subsequent action by the busmaster that owns the semaphore memory cell triggers the semaphore memory cell to switch itself to the idle state, and
• wherein a busmaster desiring ownership of the semaphore memory cell repeatedly reads the semaphore memory cell until the semaphore memory cell is owned by the busmaster desiring ownership of the semaphore memory cell.