Computer memory compression abort and bypass mechanism when cache write back buffer is full

A method for avoiding a stalled computer memory operation performed in a system implementing a processing device for enabling indirect storage and retrieval of compressed data in available address space in a physical memory associated with said system and issuing real memory addresses for accessing information from said physical memory, a cache memory array having a plurality of cache lines, a cache line write back means, associated with the cache memory array for performing a cache line fill operation by requesting and removing existing cache line data and replacing removed data with different data via a cache line write back operation, and, including a compressor mechanism for compressing processor information into compressed information units, said compressor mechanism having associated write back queue for storing data to be compressed for storage in said physical memory, wherein said stalled computer memory operation includes a cache line write back request for storing cache line data back to said physical memory via said compressor mechanism said method comprising steps of:

• comparing an occupancy state of said write back queue during a cache line write back request;
• asserting a control signal when said occupancy state indicates a full write back queue and another cache write back is initiated;
• and,
• in response to said asserted control signal, either aborting a pending compression operation when a progression status of a pending data compression operation has not exceed a data compression sequence threshold, and storing data in an uncompressed format in said physical memory to enable processing of said cache line write back request, or enabling said pending data compression operation to complete when a progression status of said pending data compression operation has exceeded said data compression sequence threshold.