Methods and apparatus for minimizing the impact of excessive instruction retrieval

An apparatus for controlling memory access requests to a memory, the apparatus comprising:

• an instruction retrieval circuit;
• and
• an interface circuit, coupled to the instruction retrieval circuit, the interface circuit including a request queue and a control circuit coupled to the request queue, wherein:
• the interface circuit queues, from the instruction retrieval circuit, a prefetch request for performing a prefetch operation that prefetches a first set of instructions from the memory, and the control circuit adds, in the request queue, a first entry identifying the prefetch operation in response to the prefetch request;
• the interface circuit subsequently queues, from the instruction retrieval circuit, a fetch request for performing a fetch operation that fetches a second set of instructions from the memory to satisfy a cache miss, and the control circuit adds, in the request queue, a second entry identifying the fetch operation in response to the to the fetch request;
• and
• the interface circuit cancels the queued prefetch request when the fetch request is received from the instruction retrieval circuit before the prefetch operation initiates in response to the queued prefetch request, and performs the prefetch operation to completion when the fetch request is received from the instruction retrieval circuit after the prefetch operation initiates in response to the obtained prefetch request.

A method for controlling memory access requests, comprising the steps of:

• acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request, the first entry identifying the prefetch operation;
• attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss;
• acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request, the second entry identifying the fetch operation;
• and
• invalidating the first entry in the request queue when the fetch request is acquired before the prefetch operation initiates, and maintaining the first entry in valid form in the request queue and performing the prefetch operation to completion when the fetch request is acquired after the prefetch operation initiates.

An apparatus for controlling memory access requests to a memory, the apparatus comprising:

• an instruction retrieval circuit having:
• a cache, and
• a control circuit, coupled to the cache, that attempts to retrieve a first set of instructions from the cache to create a cache miss, and generates, in response to the cache miss, a first series of requests including a fetch request for performing a fetch operation that fetches the first set of instructions from a memory to satisfy the cache miss;
• and
• an interface circuit, coupled to the instruction retrieval circuit, that:
• acquires a second series of requests including a prefetch request for performing a prefetch operation that prefetches a second set of instructions from the memory, and adds a first entry in a request queue in response to the prefetch request, the first entry identifying the prefetch operation, and
• after acquiring the second series of requests, acquires the first series of requests that includes the fetch request, and adds a second entry in the request queue in response to the fetch request, the second entry identifying the fetch operation;
• and
• invalidates the first entry in the request queue when the fetch request is acquired before the prefetch operation initiates, and otherwise maintaining the first entry in valid form in the request queue and performing the prefetch operation to
• completion when the fetch request is obtained after the prefetch operation initiates.

A method for controlling memory access requests, comprising the steps of:

• queuing a first memory access request for performing a first memory access operation that retrieves a first set of instructions from a memory;
• adding, in a request queue, a first entry identifying the first memory access operation in response to the first memory access request;
• subsequently queuing a second memory access request for performiing a second memory access operation that retrieves a second set of instructions from the memory to satisfy a cache miss;
• adding, in the request queue, a second entry identifying the second memory access operation in response to the second memory access request;
• and
• canceling the queued first memory access request when the second memory access request is received before the first memory access operation initiates in response to the queued first memory access request, and performing the first memory access operation to completion when the second memory access request is queued after the first memory access operation initiates in response to the received first memory access request.

An apparatus for controlling memory access requests to a memory, the apparatus comprising:

• an instruction retrieval circuit;
• and an interface circuit, coupled to the instruction retrieval circuit, the interface circuit including a request queue and a control circuit coupled to the request queue, wherein:
• the interface circuit queues, from the instruction retrieval circuit, a first memory access request for performing a first memory access operation that retrieves a first set of instructions from the memory, and the control circuit adds, in the request queue, a first entry identifying the first memory access operation in response to the first memory access request;
• the interface circuit subsequently queues, from the instruction retrieval circuit, a second memory access request for performing a second memory access operation that retrieves a second set of instructions from the memory to satisfy a cache miss, and the control circuit adds, in the request queue, a second entry identifying the second memory access operation in response to to the second memory access request;
• and
• the interface circuit cancels the queued first memory access request when the second memory access request is received from the instruction retrieval circuit before the first memory access operation initiates in response to the queued first memory access request, and performs the first memory access operation to completion when the second memory access request is received from the instruction retrieval circuit after the first memory access operation initiates in response of the queued first memory access request.