Sizing and insertion of decoupling capacitance

A method, comprising:

• identifying a plurality of noisy nodes from a plurality of power nodes in a power grid;
• placing a decoupling capacitor of a predetermined size at each of the plurality of noisy nodes;
• increasing the size of the decoupling capacitor at each of the noisy nodes to bring the noisy node to within its corresponding voltage thresholds;
• and
• optimizing the size of the decoupling capacitor at each of the noise nodes by decrementing the size of the decoupling capacitor at each of the noisy nodes by a predetermined capacitance decrement until just before the noisy node violates its corresponding voltage thresholds.

A computer readable medium containing instructions which, when executed in a processing system, causes the processing system to perform a method for inserting decoupling capacitance, comprising:

• identifying one or more noisy nodes from a plurality of power nodes in a power grid;
• placing a decoupling capacitor of a predetermined size at each of the noisy nodes;
• increasing the size of the decoupling capacitor at each noisy node to bring the noisy node to within its corresponding voltage thresholds;
• and
• decreasing the size of the decoupling capacitor at each noisy node to remove any excess decoupling capacitance, wherein the size of the decoupling capacitor at each noisy node is decreased by a predetermined decrement size until just before the noisy node violates its corresponding voltage thresholds.

An apparatus comprising

• means for evaluating a plurality of power nodes in a power grid to identify a plurality of noisy nodes;
• means for inserting a decoupling capacitor of a predetermined size at each of the noisy nodes;
• means for reducing noise at each of the noisy nodes to a corresponding tolerable range;
• and
• means for optimizing size of the decoupling capacitor at each of the noisy nodes to remove excess decoupling capacitance while keeping the noisy node within the corresponding tolerable range, comprising:
• means for decrementally decreasing the size of the decoupling capacitor at the noisy node using a predetermined decrement size, and means for re-evaluating the noisy node after each decrement.

An apparatus, comprising:

• a memory device to store configuration information;
• an input device coupled to the memory device, the input device to receive a power grid model comprising of a plurality of power nodes;
• and
• a processor coupled to the memory device and to the in put device, the processor to:
• evaluate the plurality of power nodes to identify a plurality of noisy nodes using the configuration information;
• insert a decoupling capacitor of predetermined size at each of the noisy nodes;
• reduce noise at each noisy node to a corresponding tolerable range as specified in the configuration information;
• and
• optimize the size of the decoupling capacitor at each noisy node by decrementally decreasing the size of the decoupling capacitor at each noisy node, and re-evaluating each noisy node after each decrement to keep the noisy nodes within the corresponding tolerable range.

An apparatus comprising

• a memory;
• a processor coupled to the memory, the processor executing a set of instructions to:
• evaluate a plurality of power nodes in a power grid to identify a plurality of noisy nodes;
• insert a decoupling capacitor of a predetermined size at each of the noisy nodes;
• reduce noise at each noisy node to a tolerable range;
• and
• optimize the size of the decoupling capacitor at each noisy node by repeatedly decreasing the size of the decoupling capacitor by a predetermined decrement while keeping the noisy node within the tolerable range.