US 6,445,760 B1Granted

Partially-synchronous high-speed counter circuits

AssigneeApplied Micro Circuits Corporation

InventorsSharon Lynn Weintraub, Mark Chien-Fu Lin

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Abstract

Partially-synchronous and non-integer integrated circuit counters for dividing a high-speed reference clock signal with a selectable divisor have been provided. The circuits use a high-speed synchronous counter that cycles between the use of a selectable and a fixed divisor, to give the counter circuit a selectable overall division ratio. The partially-synchronous counter circuit uses asynchronous dividers to complete the division process and to minimize power consumption. A non-integer counter circuit is provided that includes a edge select mechanism to reduce power consumption in the division process. Examples are presented with specific number of stages, and corresponding divisors and divisor ranges. Method for implementing the above-mentioned partially-synchronous and non-integer counter circuits have also been provided.

Claims31

Dependent claims

In an integrated circuit, a high-speed partially-synchronous counter circuit with selectable divisor comprising:

a high-speed counter section having a first input to accept a reference clock signal, a second input to accept divisor commands, a third input to accept a load pulse, the high-speed counter synchronously dividing the reference clock signal in response to the load pulse with a selectable divisor responsive to divisor commands, providing high-speed counter signals at an output;
a low-speed counter section having an input connected to the output of the high-speed counter to accept the high-speed counter signals, the low-speed counter asynchronously dividing the high-speed counter signals by a fixed value to provide low-speed counter signals at an output;
and
a load circuit having a first input connected to the low-speed counter output to accept the low-speed counter signals, a second input connected to the high speed counter output to accept the high-speed counter signals, a third input to accept the reference clock signal for synchronizing the high-speed counter signals to the reference clock signal, the load circuit having an output connected to the third input of the high-speed counter to provide the load pulse that is responsive to the low-speed counter signals and synchronized high-speed counter signals.

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Dependencies are inferred from the claim text.