Back to results
US 6,445,718 B1Granted
Serial interface circuit
AssigneeSony Corporation
InventorTakayasu Muto
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSony Corporation
InventorTakayasu Muto
Estimating the term…
A serial interface circuit capable of converting a large volume of data into packets based on a predetermined standard for transmission and reception and capable of performing smooth transmission and reception processing, configured so that, in a reception operation, a request packet generation circuit generates a request packet and calculates the maximum length of data of the response packet with respect to the request packet transmitted and a transaction controller compares the maximum length of data maxpl with the remaining memory amount of the response use FIFO and, when the remaining memory amount is larger than the maximum length of data, transmits the request packet. When the remaining memory amount is smaller than the maximum length of data maxpl, the output of the request packet to the link core, that is, the transmission of the request packet to the other node, is temporarily suspended until the remaining memory amount becomes larger than the maximum length of data maxpl.
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
A serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising:
Dependencies are inferred from the claim text.