Circuit, disk controller and method for calibrating a high precision delay of an input signal
AssigneeOak Technology, Inc.
InventorEric Shengquan Wu
Life of this patent
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Abstract
In a circuit to provide a high precision delay signal, an oscillator generates oscillator pulses, each with an oscillator period. A counter, in response to an enable signal, counts the oscillator pulses and outputs a count signal. The enable signal is a reference clock signal having a reference-clock period that is greater than the oscillator period. A delay generator delays an input signal to provide a sequence of incrementally delayed delay-signals. A multiplexor, in response to the count signal, selects one of the delayed signals. In another aspect of the invention, a disc controller uses the circuit to provide a high precision delay to a write data signal. Another aspect of the invention provides a method of providing the high precision delay.
Claims12
A circuit for applying a high precision delay to an input signal synchronized to a system clock, comprising:
- an oscillator generating oscillator pulses, each with an oscillator period;
- a counter, in response to an enable signal, counting said oscillator pulses and outputting a count signal, the count signal having a plurality of bits, wherein said enable signal is a reference clock signal synchronized to the system clock and having an enabling interval that is greater than each said oscillator period;
- a data latch to receive count bits representing a divided count signal and to output the divided count signal, wherein the count bits:
- comprise a subset of the plurality of bits of the count signal;
- and
- represent a value corresponding to the count signal divided by a positive integer power of two;
- a delay generator delaying the input signal to provide a sequence of incrementally delayed delay-signals;
- and
- a multiplexor that, in response to said divided count signal, selects one of said delay-signals that has a delay with respect to the input signal substantially equal to the enabling interval divided by 2N, where N is a positive integer.
A disk controller comprising:
- a servo system generating signals to cause an actuator to position a head over a target track on a disk, said servo system also generating at least one signal to cause a disk motor to rotate said disk;
- a datapath control unit receiving write data to write to said disk from a bus and outputting a write data signal of serially encoded digital data;
- and
- a control circuit for generating a write channel signal from said write data signal, including:
- an oscillator generating oscillator pulses, each with an oscillator period;
- a counter, in response to an enable signal, counting said oscillator pulses and outputting a count signal, the count signal having a plurality of bits, wherein said enable signal is said write data signal having an enabling interval that is greater than each said oscillator period;
- a data latch to receive count bits representing a divided count signal and to output the divided count signal, wherein the count bits:
- comprise a subset of the plurality of bits of the count signal;
- and
- represent a value corresponding to the count signal divided by a positive integer power of two;
- a delay generator providing a sequence of delayed write data signals;
- and
- a multiplexor that, in response to said divided count signal, selects one of said delayed write data signals that has a delay with respect to the write data signal substantially equal to the enabling interval divided by 2N, where N is a positive integer, to generate a write channel signal to send to said head.
A method of applying a high precision delay to an input signal synchronized to a system clock, comprising:
- generating oscillator pulses;
- counting said oscillator pulses, during an enabling interval of a reference clock signal synchronized to the system clock, to output a count signal;
- wherein the enabling interval is greater than an oscillator period associated with the oscillator pulses;
- generating a divided count signal corresponding to the count signal divided by a positive integer power of two;
- delaying the input signal to provide a sequence of delayed signals;
- and
- selecting one of said delayed signals that has a delay with respect to the input signal substantially equal to the enabling interval divided by 2N in response to said divided count signal, where N is a positive integer.
Dependencies are inferred from the claim text.