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US 6,445,644 B2Granted
Apparatus and method for generating a clock within a semiconductor device and devices and systems including same
AssigneeMicron Technology, Inc.
InventorJoseph C. Sher
Life of this patent
Estimating the term…
Abstract
A clock generator which provides a stable, programmable pulse width output clock signal based on an input clock signal. The clock generator provides a leading edge of an output clock signal in response to a leading edge of an input clock signal. The trailing edge of the output clock signal is conditioned on feedback of the leading edge output clock signal with the trailing edge of the input signal.
Claims36
A clock generator comprising:
- a latch for receiving an input clock signal;
- a delay path operably coupled to the latch for propagating a leading pulse edge of the input clock signal to an input of the latch and outputting a corresponding leading pulse edge of an output clock signal, said delay path including a programmable delay element;
- and
- a feedback path interposed between the delay path and the latch for returning the leading pulse edge of the output clock signal to the latch to reset the latch and cause the delay path to propagate and output a trailing pulse edge of the output clock signal.
1 more element
A clock generator comprising:
- a NAND gate for receiving an input clock signal;
- an output switching circuit operably coupled to said NAND gate for outputting a leading pulse edge of an output clock signal in response to a leading pulse edge of an input clock signal;
- and
- a feedback circuit including a programmable delay element interposed between said NAND gate and said output switching circuit for delaying said leading pulse edge of the output clock signal and selectively resetting said NAND gate in response to said delayed leading pulse edge of said output clock signal to propagate a trailing pulse edge of said output clock signal through said output switching circuit.
1 more element
An input buffer comprising:
- a latch for receiving an input clock signal;
- an output switching circuit operably coupled to said latch for outputting a leading pulse edge of an output clock signal in response to a leading pulse edge of said input clock signal latched by said latch and returning said output leading pulse edge to an input of said latch;
- and
- a feedback circuit interposed between said latch and said output switching circuit including a programmable delay element for selectively delaying said leading pulse edge of said output clock signal and selectively resetting said latch in response to said delayed leading pulse edge of said output clock signal to selectively propagate a trailing pulse edge of said output clock signal through said output switching circuit.
1 more element
A semiconductor memory including a clock generator, said clock generator comprising:
- a latch for receiving an input clock signal;
- an output switching circuit operably coupled to an output of said latch for outputting a leading pulse edge of an output clock signal in response to a leading pulse edge of said input clock signal and returning said output leading pulse edge to an input of said latch;
- and
- a feedback circuit interposed between said latch and said output switching circuit including a programmable delay element for selectively delaying said leading pulse edge of said output clock signal and selectively resetting said latch in response to said selectively delayed leading pulse edge of said output clock signal to selectively propagate a trailing pulse edge of said output clock signal through said output switching circuit.
1 more element
An electronic system comprising an input device, an output device, a memory device, and a processor device operably coupled to said input, said output, and said memory devices, said memory device including a clock generator comprising:
- a latch for receiving an input clock signal;
- an output switching circuit operably coupled to an output of said latch for outputting a leading pulse edge of an output clock signal in response to a leading pulse edge of said input clock signal and returning said output leading pulse edge to an input of said latch;
- and
- a feedback circuit interposed between said latch and said output switching circuit including a programmable delay element for selectively delaying said leading pulse edge of said output clock signal and selectively resetting said latch in response to said selectively delayed leading pulse edge of said output clock signal to selectively propagate a trailing pulse edge of said output clock signal through said output switching circuit.
1 more element
A semiconductor substrate having a clock generator fabricated thereon, said clock generator comprising:
- a latch for receiving an input clock signal;
- an output switching circuit operably coupled to an output of said latch for outputting a leading pulse edge of an output clock signal in response to a leading pulse edge of said input clock signal and returning said output leading pulse edge to an input of said latch;
- and
- a feedback circuit interposed between said latch and said output switching circuit including a programmable delay element for selectively delaying said leading pulse edge of said output clock signal and selectively resetting said latch in response to said selectively delayed leading pulse edge of said output clock signal to selectively propagate a trailing pulse edge of said output clock signal through said output switching circuit.
1 more element
A method of generating a clock signal comprising:
- providing a latch for receiving an input clock signal;
- providing a programmable delay path for propagating a leading pulse edge of said input clock signal and outputting a corresponding leading pulse edge of an output clock signal;
- providing a feedback path for returning said leading pulse edge of said output clock signal to said latch and outputting a trailing pulse edge of said output clock signal.
A method of generating a clock signal comprising:
- latching a leading edge of an input clock signal;
- outputting a leading edge of an output clock signal in response to said leading edge of said input clock signal;
- returning and selectively delaying said leading edge of the output clock signal;
- and
- outputting a trailing edge of said output clock signal in response to said delayed leading edge of said output clock signal.
2 more elements
A method of generating a delayed pulse signal using an electronic circuit including a NAND gate, a delay path, and a feedback path, said method comprising:
- latching an input clock signal with said NAND gate;
- outputting a leading edge of an output clock signal through said delay path;
- returning and selectively delaying said leading edge of said output clock signal to said NAND gate through said feedback path;
- and
- outputting a trailing edge of said output clock signal in response to said delayed leading edge of said output clock signal.
2 more elements
Dependencies are inferred from the claim text.