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US 6,445,643 B2Granted
Method and apparatus for setting write latency
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson
Estimating the term…
A method of setting write latency and a write/valid indicator circuit for use with the method. In a preferred embodiment, time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. The write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.
A write/valid indicator circuit for a synchronous dynamic random access memory circuit (SDRAM), the write/valid indicator circuit comprising:
A write/valid indicator circuit for a synchronous dynamic random access memory circuit (SDRAM), the write/valid indicator circuit comprising:
A dynamic random access memory circuit (DRAM) comprising:
An electronic system comprising:
A semiconductor substrate comprising a DRAM having a write/valid indicator circuit comprising:
A write/valid indicator circuit for a synchronous dynamic random access memory circuit (SDRAM), the write/valid indicator circuit comprising:
A write/valid indicator circuit for a synchronous dynamic random access memory circuit (SDRAM), the write/valid indicator circuit comprising:
A write/valid indicator circuit for a synchronous dynamic random access memory circuit (SDRAM), the write/valid indicator circuit comprising:
A dynamic random access memory circuit (DRAM) comprising:
A dynamic random access memory circuit (DRAM) comprising:
A dynamic random access memory circuit (DRAM) comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: control signal input…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
Term ended 9 Feb 2020 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates generally to a method and apparatus for setting write latency in a memory system. More particularly, the present invention relates to a write latency procedure and apparatus which reduce the risk of data stored in memory being defective due to the memory improperly receiving a write enable signal too early or too late in relation to the data and the preamble of the data clock to compensate for timing variations occurring after initialization.
2. State of the Art
The nature of the present invention as well as other embodiments of the present invention may be more clearly understood by reference to the following detailed description of the invention, to the appended claims, and to several drawings herein, wherein:
FIG. 1 is a timing diagram of a prior art DRAM memory write enable process comparing the DCLK, write enable (RxEn) and Data signals.
FIG. 2 is a diagram of a prior art DRAM receiver.
FIG. 3 illustrates five general timing categories of write enable signals (RxEn) with respect to a DCLK signal 8. The RxEn (Early) signal 12 is a signal which transitions before the preamble 6 of the DCLK signal 8. The RxEn (Marginally Early) signal 14 is a signal which transitions within the preamble 6, but near the start 16 of the preamble 6. The RxEn (Centered) signal 18 is a signal which transitions within the preamble 6, but not near either the start 16 or the end 20 of the preamble 6. The RxEn (Marginally Late) signal 22 is a signal which transitions within the preamble 6, but near the end 20 of the preamble 6. The RxEn (Late) signal 24 is a signal which transitions after the preamble 6 of the DCLK signal 8. As briefly described above, one problem that occurs using prior art write latency settings is that as the system warms up, signal timing may shift, resulting in problems with the initial latency settings. The presently acceptable range of latency settings include settings where the write enable signal (RxEn) transitions near the start 16 or end 20 of the preamble 6. If the latency setting established during initialization is one where the write enable signal (RxEn) transitions near the start 16 or end 20 of the preamble 6, such as RxEn (Marginally Early) 14 or RxEn (Marginally Late) 22, when the system warms up, the write enable signal may shift far enough so as to not transition within the preamble.
FIG. 4 depicts a timing diagram of a DRAM write enable process of the present invention wherein time margin regions 26 near the first or leading edge or start 16 and second or following edge or end 20 of the preamble 6 of the DCLK signal 8 are preselected for a system as being an unacceptable range within the preamble 6 for the write enable signal (RxEn) to transition. Not only does the write enable signal (RxEn) need to transition within the preamble 6 to be acceptable for the preferred embodiments of the present invention, but it is preferable that it not transition within either of the time margin regions 26. As will be clear from the following disclosure, however, the time margin regions 26 may be adjusted to as large or as small as needed for a specific application so long as the time margin regions 26 themselves do not overlap. In this way, the process adapts for the postinitialization changes in a system by selecting a latency setting which allows for a buffer zone in which the write enable signal (RxEn) may shift with respect to the DCLK preamble boundaries without shifting outside of the preamble 6.
FIG. 5 is a block diagram of a write/valid indicator circuit 28 for use in setting latency in an embodiment of the present invention comprising first delay 30, second delay 32, first priority circuit 34, second priority circuit 36 and evaluator circuit 38. According to the present embodiment, the first delay 30 delays a clock signal (DCLK) 40 (also referred to as “DCLK signal 40”) by a predetermined time T1. The first priority circuit 34 then receives both the delayed DCLK signal 40 and an undelayed write enable (RxEn) signal 42 and compares the signals to determine whether the leading edge 50 (FIG. 6) of the preamble 52 of delayed DCLK signal 40 transitioned low prior to the undelayed write enable (RxEn) signal 42 transitioning high. If the delayed DCLK signal 40 transitioned low before the undelayed write enable (RxEn) signal 42 transitioned high, the first priority circuit 34 indicates this with a signal to the evaluator circuit 38. By comparing a write enable (RxEn) signal 42 with the DCLK signal 40 delayed by time T1, and indicating when the delayed DCLK signal 40 transitions low first, the first priority circuit 34 ensures that undelayed write enable (RxEn) signal 42 has transitioned at least time T1 away from the leading edge 50 of the preamble 52 (FIG. 6). In this way, as depicted in FIG. 6, write/valid indicator circuit 28 sets a first time margin region 48 near the leading edge 50 of the DCLK signal 40 preamble 52. In other words, if the write enable (RxEn) signal 42 transitions high 54 within the first time margin region 48 or prior to the preamble 52, the first priority circuit 34 (FIG. 5) will indicate the write enable (RxEn) signal 42 as transitioning high 54 within an unacceptable portion of the preamble 52 and will, therefore, indicate the present latency setting is unacceptable.