Synchronous double data rate DRAM
AssigneeNEC Corporation
InventorNaoki Murakami
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Abstract
A DDR-SDRM includes a data write section including a latch section for latching first write data at a rising edge of a data strobe signal and second write data at a falling edge of the data strobe signal, and a write buffer section for writing the first write data and the second write data at a time based on the signals generated from the data strobe signal. A read operation is conducted based on the system clock signal.
Claims17
A double data rate synchronous DRAM (DDR-SDRM) comprising a memory cell array including a plurality of memory cells, an address signal processing section for receiving and processing an address signal for specifying an address of one of said memory cells, said address signal processing section operating in synchrony with a system clock signal, a data write section for receiving write data and writing the write data into said one of said memory cells in a write cycle, and a data read section for responding to said system clock signal to read data from said one of said memory cells in a read cycle to deliver read data, said data write section operating based on a data strobe signal transferred in synchrony with said write data to receive said write data from outside said DDR-SDRM and deliver said write data through I/O lines to said one of said memory cells.
A double data rate synchronous DRAM (DDR-SDRM) comprising a memory cell array including a plurality of memory cells, an address signal processing section for receiving and processing an address signal for specifying an address if one of said memory cells, said address signal processing section operating in synchrony with a system clock signal, a data write section for receiving write data and writing the write data into said one of said memory cells in a write cycle, and a data section for responding to said system clock signal to read data from said one of said memory cells in a read cycle to deliver read data, wherein said data write section includes a data latch section for receiving said write data from outside said DDR-SDRM and a write buffer section for writing said write data to said one of said memory cells, and said data write section operating based on a data strobe signal transferred in synchrony with said write data to receive said write data from outside said DDR-SDRM and deliver said write data through I/O lines to said one of said memory cells.
Dependencies are inferred from the claim text.