Memory device with time shared data lines
AssigneeG-Link Technology
InventorJong-Hoon Oh
Life of this patent
Estimating the term…
Abstract
A memory device having an array of memory cells distributed into rows and columns with a plurality of interconnects extending across the array and coupled to carry write data during a first period of time and control data during a second period of time. In some embodiments where data I/O pads, input buffers, I/O sense amplifiers, write drivers, and color registers are collectively located on an opposite side of the array away from column decoders, column pre-decoders and column redundancy circuits, time-sharing of write data and control data on a single bus significantly improves layout efficiency.
Claims25
A memory device comprising:
- an array of memory cells distributed in rows and columns;
- a plurality of interconnects extending across the array and coupled to carry write data during a first period of time and control data during a second period of time,
- wherein, the control data includes column mask information for block write operations.
A method of operating a memory device comprising the steps of:
- receiving column mask information on input nodes located at one end of an array of memory cells;
- driving column mask information onto array-long interconnect lines to supply column mask information to circuitry across the array of memory cells during a first period of time;
- and
- driving write data onto the interconnect lines to supply write data to the array of memory cells during a second period of time that is different than the first period of time.
A memory device comprising:
- an array of memory cells distributed in rows and columns;
- a plurality of write drivers located on a first side of the array and coupled to data input pads;
- a plurality of data buses coupled to the plurality of write drivers and extending across the array coupling to the memory cells inside the array;
- a column decoder array located on a second side opposite to the first side of the array and coupled to the plurality of data buses;
- and
- block write control circuit coupled to a predetermined write driver and configured to deliver column mask information to the predetermined write driver to be driven onto a respective data bus during a first period of a block write operation, and to deliver a corresponding color data to the predetermined write driver to be driven onto the respective data bus during a second period of the block write operation.
Dependencies are inferred from the claim text.