Integrated dynamic semiconductor memory with time controlled read access

An integrated dynamic semiconductor memory, comprising:

• a memory cell array configured as a matrix and including memory cells;
• column lines and row lines;
• said memory cells being combined to form addressable units with said column lines and said row lines;
• a decoder generating a selection signal;
• a selection signal line connected to said decoder and running across said memory cell array for transmitting the selection signal for selecting one of said column lines;
• a sense amplifier having an input, said sense amplifier being jointly allocated to all of given ones of said memory cells provided in a selected one of said column lines, said memory cells being disposed between said decoder and said sense amplifier;
• a data signal line for transmitting a data signal of one of said memory cells present on said selected one of said column lines across said memory cell array, the data signal being an amplified data signal;
• said input of said sense amplifier being connected to said data signal line for further processing the data signal;
• and
• said memory cell array having an edge and having opposite sides, said decoder and said sense amplifier being disposed at said edge and respectively on said opposite sides of said memory cell array.