Folded-bitline dual-port DRAM architecture system

A multi-port dynamic random access memory (DRAM) architecture system capable of suppressing noise due to the bitline-to-bitline coupling effect, the system comprising:

• a plurality of dynamic random access memory (DRAM) cells arranged in an array, each of the DRAM cells having a corresponding first port and a corresponding second port, each first and second port enabling access to the corresponding DRAM cell;
• and
• a complementary bitline for every bitline of the array, wherein each complementary bitline traverses the array in twisted configuration with respect to a corresponding bitline, wherein, during a signal developing period and a signal sensing period, the complementary bitline is coupled to a higher voltage level and its corresponding bitline is coupled by the same amount to a lower voltage level, and vice versa, thereby canceling out the bitline-to-bitline coupling effect.

A method of suppressing noise due to the bitline-to-bitline coupling effect in a multi-port dynamic random access memory (DRAM) array having a plurality of DRAM cells, the method comprising the step of:

• providing a complementary bitline for each bitline of the array, wherein each complementary bitline traverses the array in twisted configuration with respect to a corresponding bitline, wherein, during a signal developing period and a signal sensing period, the complementary bitline is coupled to a higher voltage level and its corresponding bitline is coupled by the same amount to a lower voltage level, and vice versa, thereby canceling out the bitline-to-bitline coupling effect.

A method of suppressing noise due to the wordline-to-bitline coupling effect in a multi-port dynamic random access memory (DRAM) array having a plurality of DRAM cells, the method comprising the step of:

• providing a complementary bitline for each bitline of the array to form a plurality of complementary bitline and bitline pairs, at least one wordline traverses the array and intersects at least one pair of the plurality of complementary bitline and bitline pairs, wherein, during a wordline activation period, the coupling between the wordline and the bitline of the at least one pair and the wordline and complementary bitline of the at least one pair are equal, thereby canceling out the wordline-to-bitline coupling effect.

A multi-port dynamic random access memory (DRAM) architecture system capable of suppressing noise due to the bitline-to-substrate coupling effect, the system comprising:

• a plurality of dynamic random access memory (DRAM) cells arranged in an array and fabricated on a substrate, each of the DRAM cells having a corresponding first port and a corresponding second port, each first and second port enabling access to the corresponding DRAM cell;
• and
• a complementary bitline for each bitline of the array forming a plurality of complementary bitline and bitline pairs, one of the bitlines of each pair couples the substrate to a higher voltage level and the other bitline of each pair couples the substrate by the same amount to a lower voltage level during a signal developing period and a signal sensing period, thereby canceling out the bitline-to-substrate coupling effect.

A method of suppressing noise due to the bitline-to-substrate coupling effect in a multi-port dynamic random access memory (DRAM) array having a plurality of DRAM cells fabricated on a substrate, the method comprising the step of:

• providing a complementary bitline for each bitline of the array to form a plurality of complementary bitline and bitline pairs, one of the bitlines of each pair couples the substrate to a higher voltage level and the other bitline of each pair couples the substrate by the same amount to a lower voltage level during a signal developing period and a signal sensing period, thereby canceling out the bitline-to-substrate coupling effect.