Method and system for hiding refreshes in a dynamic random access memory

A dynamic random access memory (“DRAM”), comprising:

• a first array of memory cells, the first array storing data;
• a second array of memory cells, the second array containing substantially the same data as the data stored in the first array;
• an address circuit to receive an address and being structured to access locations in the first and second arrays corresponding to the address;
• a data path circuit structured to couple data between a data terminal and the first and second arrays;
• a control circuit;
• and
• a refresh circuit coupled to the control circuit and the first and second arrays, the refresh circuit being structured to refresh the memory cells in either the first array or the second array, the refresh circuit being structured to permit data to be written to the first array when the second array is being refreshed and to permit data to be written to the second array when the first array is being refreshed.

A computer system, comprising:

• a processor coupled to a processor bus;
• a memory controller coupled to the processor bus;
• a system memory coupled to memory controller for allowing memory accesses by the processor;
• a data input device coupled to the processor;
• a data output device coupled to the processor;
• and
• a cache memory coupled to the processor through the processor bus, the cache memory being a dynamic random access memory (“DRAM”) comprising:
• a first array of memory cells;
• a second array of memory cells;
• an address circuit to receive an address and being structured to access locations in the first and second arrays corresponding to the address;
• a data path circuit structured to couple data between a data terminal and the first and second arrays;
• a control circuit to receive memory commands and being structured to generate control signals corresponding to the memory commands to access the first and second arrays;
• and
• a refresh circuit coupled to the control circuit and the first and second arrays, the refresh circuit being structured to refresh the memory cells in either the first array or the second array, the refresh circuit being structured to cause write data to be temporarily stored in a write buffer responsive to a write memory access when either the first or second arrays is being refreshed, to determine when the refresh is completed, and to transfer the data from the write buffer to the array that was being refreshed after the refresh has been completed.

A method of refreshing a dynamic random access memory (“DRAM”) while substantially hiding the refresh, the method comprising:

• storing data in a first array of memory cells;
• storing substantially the same data that is stored in the first array of memory cells in a second array of memory cells having substantially the same size as the first array;
• refreshing the memory cells in either the first array or the second array, but not both arrays at the same time;
• and
• allowing memory accesses to one of the first and second arrays as a function of either whether the first array is being refreshed and whether the second array is being refreshed.

A method of refreshing a dynamic random access memory (“DRAM”) while substantially hiding refresh, the method comprising:

• storing data in a first array of memory cells;
• storing substantially the same data that is stored in the first array of memory cells in a second array of memory cells having substantially the same size as the first array;
• refreshing the memory cells in either the first array or the second array, but not both arrays at the same time;
• permitting data to be written to the first array when the second array is being refreshed;
• and
• permitting data to be written to the second array when the first array is being refreshed.

The method of claim 50further comprising:

• determining if either of the first and second arrays is being refreshed;
• permitting data be written to the array that is not being refreshed;
• if either of the first and second arrays is being refreshed, temporarily storing the data that is to be written to the array that is being refreshed;
• waiting until the refresh of the array has been completed;
• and
• after the refresh has been completed, permitting the data to be written to the array that was being refreshed.