High speed asynchronous and programmable state machine for generating almost empty synchronous flags in a synchronous FIFO

An apparatus comprising:

• a first set state machine having a first input receiving a first write clock, a second input receiving a first read clock, a third input receiving a first programmable Almost Empty look-ahead signal, and a fourth input to receive a first control signal;
• said first set state machine manipulating said inputs to produce a first set_output signal that is either at a first logic state or at a second logic state;
• a second set state machine having a first input receiving a second write clock, a second input receiving a second read clock, a third input receiving a second programmable Almost Empty look-ahead signal, and a fourth input to receive a second control signal;
• said second set state machine manipulating said inputs to produce a second set_output signal that is either at said first logic state or at said second logic state;
• a synchronizer coupled to said second set state machine, said synchronizer receiving said second set_output signal and receiving a reset signal;
• said synchronizer configured to generate a synchronized output signal;
• a latch having a first input receiving said first set_output signal, a second input receiving said synchronized output signal, a first latch_output presenting said first set_output signal as a first latch_output signal, and a second latch_output presenting said synchronized output signal as a second latch_output signal, said latch being configured to hold said first latch_output signal and said second latch_output signal until said first set_output signal and second set output signal change logic states, said first latch_output signal representing an Almost Empty output flag that is at a first logic state when a FIFO (First In First Out) memory block is Almost Empty, and is at a second logic state when said FIFO is Not Almost Empty;
• said second latch_output signal representing said Not Almost Empty output flag that is at said first logic state when said FIFO is Not Almost Empty and is at said second logic state when said FIFO is Almost Empty;
• a first logic block having a logic input receiving said second latch_output signal, and a logic output presenting said second latch_output signal as said first control signal to said first set state machine;
• and
• a second logic block having a logic input receiving said first latch_output signal, a first logic output presenting said first latch_output signal as said second control signal to said second set state machine;
• and a second logic output presenting said first latch_output signal as said reset signal to said synchronizer.

A method for indicating the almost empty status of at least one memory buffer comprising the steps of:

• generating at least one Almost Empty output flag in response to a plurality of signals comprising:
• a first write clock, a first read clock, a first programmable Almost Empty look-ahead signal, a second write clock, a second read clock, and a second programmable Almost Empty look-ahead signal;
• generating at least one Not Almost Empty output flag in response to said plurality of signals ;
• and
• presenting said first write clock, said first read clock, said first programmable Almost Empty look-ahead signal, said second write clock, said second read clock, and said second programmable Almost Empty look-ahead signal to a state machine, wherein said state machine generates said at least one Almost Empty output flag and said at least one Not Almost Empty output flag.

An apparatus comprising:

• a first manipulating means for receiving a first plurality of input signals comprising:
• a first write clock, a first read clock, a first programmable Almost Empty look-ahead signal, and a first control signal;
• said first means manipulating said first plurality of input signals to produce a first output signal that is either at a first logic state or at a second logic state;
• a second manipulating means for receiving a second plurality of input signals comprising:
• a second write clock, a second read clock, a second programmable Almost Empty look-ahead signal, and a second control signal;
• said second means manipulating said second plurality of input signals to produce a second output signal that is either at a first logic state or at a second logic state;
• a synchronizer means for synchronizing said first output signal and said second output signal, said synchronizer means configured to receive said second output signal and configured to receive a reset signal;
• said synchronizer means configured to generate a synchronized output signal;
• a latch means configured to receive said first set_output signal, and said synchronized output signal, said latch means configured to present said first output signal as a first latch_output signal, and said synchronized output signal as a second latch_output signal, said first latch_output signal representing an Almost Empty output flag that is at a first logic state when a FIFO memory block is Almost Empty, and is at a second logic state when said FIFO is Not Almost Empty;
• said second latch_output signal representing said Not Almost Empty output flag that is at said first logic state when said FIFO is Not Almost Empty and is at said second logic state when said FIFO is Almost Empty;
• a first logic means configured to receive said second latch_output signal, and configured to present said second latch_output signal as a first control signal to said first manipulating means;
• and
• a second logic means configured to receive said first latch_output signal, configured to present said first latch_output signal as said second control signal to said second manipulating means, and configured to present said first latch_output signal as said reset signal to said synchronizer means.