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US 6,445,631 B1Granted
Non-volatile latch with program strength verification
AssigneeNational Semiconductor Corporation
InventorGregory J. Smith
Life of this patent
Estimating the term…
Abstract
An improved approach to examining program strength of non-volatile latches is disclosed. The program strength is able to be evaluated by inferring floating gate charge of memory elements of the non-volatile latches as indicated by current characteristics of the memory elements. Access to the program charge or the internal currents is facilitated by monitoring circuitry provided integral with the non-volatile latches.
Claims12
A non-volatile memory circuit, comprising:
- a first floating gate transistor having a drain terminal, a source terminal, a control gate terminal, and a charge injection terminal, the drain terminal being coupled to a first node, the source terminal being coupled to a first potential, the gate terminal being coupled to a first set potential, and the charge injection terminal being coupled to a second set potential;
- a second floating gate transistor having a drain terminal, a source terminal, a control gate terminal, and a charge injection terminal, the drain terminal being coupled to a second node, the source terminal being coupled to the first potential, the gate terminal being coupled to the second set potential, the charge injection terminal being coupled to the first set potential;
- a first latch transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to a second potential, and the gate terminal being coupled to the second node;
- a second latch transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to the second potential, and the gate terminal being coupled to the first node;
- a first test transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to a first test line, and the gate terminal being coupled to a second test line;
- a second test transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the second node, the source terminal being coupled to the first test line, and the gate terminal being coupled to a third test line;
- and
- an output buffer coupled to the second node for providing an output of said non-volatile memory circuit.
5 more elements
An integrated circuit, comprising:
- is a first non-volatile latch providing a pair of first memory cells that together provide a first bit of memory;
- a first pair of test selectors respectively controllably coupled to the pair of said first memory cells;
- a second non-volatile latch providing a pair of second memory cells that together provide a second bit of memory;
- a second pair of test selectors respectively controllably coupled to the pair of said second memory cells;
- a third non-volatile latch providing a pair of third memory cells that together provide a third bit of memory;
- a third pair of test selectors respectively controllably coupled to the pair of said first memory cells;
- a first test line operatively connected to said first pair of test transistors;
- a second test line operatively connected to one of the test selectors of said first pair of transistors;
- and
- a third test line operatively connected to another of the test selectors of said first pair of transistors.
7 more elements
Dependencies are inferred from the claim text.