Column redundancy architecture system for an embedded DRAM

A bitline column redundancy architecture system for an embedded DRAM (eDRAM) system comprising:

• an eDRAM array comprising:
• a plurality of memory cell blocks having a plurality of bitlines traversing there through, each of said plurality of memory cell blocks includes a bitline redundancy block having at least one redundancy bitline for replacing at least one defective bitline of the plurality of bitlines;
• a plurality of sense amplifiers each coupled to corresponding bitlines of the plurality of bitlines;
• and
• a plurality of datalines, including a group of redundancy datalines, coupled to corresponding sense amplifiers of the plurality of sense amplifiers;
• and
• a memory device for storing column addresses corresponding to memory cell blocks of the plurality of memory cell blocks having at least one defective bitline traversing there through.

A method for reading data to an I/O data interface of an eDRAM architecture system having an eDRAM and a plurality of memory cell blocks, the method comprising the steps of:

• receiving an incoming address having a micro cell block address bit field and a row address bit field;
• comparing the micro cell block address bit field with a micro cell block address bit field corresponding to the row address bit field and stored in a first memory;
• if the two micro cell block address bit fields are identical, then:
• using the row address bit field to select a corresponding row in an SRAM cache;
• and
• transferring data stored in the selected row to the I/O data interface;
• and
• if the two micro cell block address bit fields are not identical, then:
• using the micro cell block address bit field of the incoming address to obtain a fuse column address and a corresponding fuse valid bit from a second memory;
• determining a logic state of the fuse valid bit;
• transferring data from a micro cell block of the plurality of micro cell blocks corresponding to the obtained column address to the SRAM cache and transferring data from the SRAM cache to the I/O interface, if the logic state of the fuse valid bit is low;
• and
• using the obtained column address for selecting and replacing at least one non-redundancy dataline of a plurality of datalines of the eDRAM architecture system with at least one redundancy dataline, transferring data from the eDRAM via non-replaced datalines of the plurality of datalines and the at least one redundancy dataline to the SRAM cache, and transferring data from the SRAM cache to the I/O interface, if the logic state of the fuse valid bit is high.

A method for writing new data to an SRAM cache of an eDRAM architecture system having an eDRAM and a plurality of memory cell blocks, the method comprising the steps of:

• receiving an incoming address having a micro cell block address bit field and a row address bit field;
• comparing the micro cell block address bit field with a micro cell block address bit field corresponding to the row address bit field and stored in a first memory;
• if the two micro cell block address bit fields are identical, then:
• using the row address bit field to select a corresponding row in an SRAM cache;
• and
• transferring new data from an I/O data interface to the selected row of the SRAM cache;
• and
• if the two micro cell block address bit fields are not identical, then:
• using the micro cell block address bit field corresponding to the row address bit field to obtain a fuse column address and a corresponding fuse valid bit from a second memory;
• determining a logic state of the fuse valid bit;
• transferring old data stored within a row of the SRAM cache corresponding to the row address bit field to the eDRAM and transferring new data to the SRAM cache from the I/O data interface, if the logic state of the fuse valid bit is low;
• and
• using the obtained fuse column address for selecting and replacing at least one non-redundancy dataline of a plurality of datalines of the eDRAM architecture system with at least one redundancy dataline, transferring old data stored within the row of the SRAM cache corresponding to the row address bit field to the eDRAM via non-replaced datalines of the plurality of datalines and the at least one redundancy dataline, and transferring new data to the SRAM cache from the I/O interface, if the logic state of the fuse valid bit is high.