US 6,445,625 B1 · Memory device redundancy selection having test inputs

A redundancy match signal latch circuit, comprising:

a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;
a latch input for providing a redundancy match signal to the pair of reverse-coupled inverters;
and
a latch output for providing a latched match signal from the pair of reverse-coupled inverters;
wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal;
wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal;
and
wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal.

5 more elements

A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
and
addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;
wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either a redundancy match signal or a test input signal;
wherein a logic level of the latched match signal is independent of the logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal;
and
wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

9 more elements

A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
and
addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a feedforward inverter having an input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing an inverted first signal as a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

7 more elements

A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
and
addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a NAND gate having a first input for receiving a first signal, a second input for receiving a second signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

7 more elements

A memory device, comprising:

a memory array having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
and
addressing circuitry coupled to the memory array for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a multiplexer having an inverted first input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, at least one additional input each for receiving a test input signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a feedback inverter having an input for receiving the feedforward signal and an output for providing the feedback signal as an inverted feedforward signal;
wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

8 more elements

A synchronous flash memory device, comprising:

an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device and commands generated by the command execution logic, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;
wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal;
wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal;
and
wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

10 more elements

A synchronous flash memory device, comprising:

an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device and commands generated by the command execution logic, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a feedforward inverter having an input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing an inverted first signal as a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

8 more elements

A synchronous flash memory device, comprising:

an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device and commands generated by the command execution logic, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a NAND gate having a first input for receiving a first signal, a second input for receiving a second signal that is selectively either the redundancy match signal or a feedback signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a multiplexer having an inverted first input, at least one additional input, and an output for providing the feedback signal, wherein the inverted first input is coupled to receive the feedforward signal and each additional input is coupled to receive a test input signal, further wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

8 more elements

A synchronous flash memory device, comprising:

an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device and commands generated by the command execution logic, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a multiplexer having an inverted first input for receiving a first signal that is selectively either the redundancy match signal or a feedback signal, at least one additional input each for receiving a test input signal, and an output for providing a feedforward signal, wherein the latched match signal is derived from the feedforward signal;
and
a feedback inverter having an input for receiving the feedforward signal and an output for providing the feedback signal as an inverted feedforward signal;
wherein the multiplexer is responsive to at least one control signal to selectively couple its output to either its first input or one of the at least one additional inputs;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level.

9 more elements

A synchronous flash memory assembly, comprising:

a memory package having a plurality of interconnects;
and
a synchronous flash memory device contained in the memory package, wherein the synchronous flash memory device comprises:
an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device, wherein the addressing circuitry selectively accesses either a primary grouping of memory cells or a redundant grouping of memory cells in response to a latched match signal from a latch circuit, the latch circuit comprising:
a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;
wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either a redundancy match signal or a test input signal, the redundancy match signal having a first logic level when the location address matches a known defective address and a second logic level when the location address does not match the known defective address;
wherein a logic level of the latched match signal is independent of the logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal;
and
wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal.

9 more elements

A synchronous flash memory assembly, comprising:

a memory package having a plurality of interconnects;
and
a synchronous flash memory device contained in the memory package, wherein the synchronous flash memory device comprises:
an array of non-volatile flash memory cells having at least one primary grouping of memory cells and at least one redundant grouping of memory cells;
a command execution logic coupled to the array of non-volatile flash memory cells for receiving at least a system clock input signal and for generating commands to control operations performed on the array of non-volatile flash memory cells, wherein the commands are synchronized to the system clock input signal;
and
addressing circuitry coupled to the array of non-volatile flash memory cells for accessing a target memory cell in response to a location address applied to the memory device and commands generated by the command execution logic, wherein the addressing circuitry has a redundancy selection circuit, the redundancy selection circuit comprising:
a latch circuit having an input for receiving a redundancy match signal and an output for providing a latched match signal, the latch circuit comprising:
a pair of reverse-coupled inverters having a first inverter and a second inverter, wherein the first inverter has at least one test input, each for receiving a test input signal;
wherein the first inverter is responsive to one or more control signals to cause the pair of reverse-coupled inverters to generate the latched match signal from either the redundancy match signal or a test input signal;
wherein a logic level of the latched match signal is independent of a logic level of the redundancy match signal when the pair of reverse-coupled inverters generates the latched match signal from a test input signal;
and
wherein a logic level of the latched match signal is independent of a logic level of any test input signal when the pair of reverse-coupled inverters generates the latched match signal from the redundancy match signal;
a redundant element access device, wherein the redundant element access device is responsive to the latched match signal to access a redundant grouping of memory cells when the latched match signal has a first logic level and to suppress access to the redundant grouping of memory cells when the latched match signal has a second logic level, further wherein the latched match signal has the first logic level when the location address matches a known defective address and has the second logic level when the location address does not match a known defective address;
and
a primary element access device, wherein the primary element access device is responsive to a second control signal to selectively access a primary grouping of memory cells when the latched match signal has the second logic level and wherein access to the primary grouping of memory cells by the primary element access device is suppressed regardless of a logic level of the second control signal when the latched match signal has the first logic level;
address inputs coupled between the memory array and a first portion of the plurality of interconnects of the memory package;
data inputs/outputs coupled between the memory array and a second portion of the plurality of interconnects of the memory package;
power inputs coupled between the memory array and a third portion of the plurality of interconnects of the memory package;
clock and control signal inputs coupled between the memory array and a fourth portion of the plurality of interconnects of the memory package;
and
a command execution logic coupled to the memory array for receiving at least a system clock input signal from the clock and control signal inputs and for generating commands to control operations performed on the memory array synchronized to the system clock input signal.

19 more elements

Memory device redundancy selection having test inputs

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Memory device redundancy selection having test inputs

Life of this patent

Abstract

Claims38