Method of synchronizing read timing in a high speed memory system

A memory module comprising:

• a plurality of memory devices, wherein each of said memory devices further comprises,
• a memory array;
• at least one data signal line coupled to said memory array;
• a control circuit;
• a read clock signal line coupled to said control circuit for receiving a read clock signal;
• a flag signal line coupled to said control circuit for receiving a flag signal;
• at least one command signal line coupled to said control circuit for receiving a read command;
• and
• wherein said control circuit causes the memory device to output data from said array associated with a previously accepted command on said at least one data signal line, beginning at a predetermined number of read clock cycles after the control circuit receives the flag signal.

A computer system comprising:

• a processor;
• a memory controller coupled to the processor;
• a first memory module having a first plurality of memory devices wherein said first plurality of memory devices includes a first read clock signal line for receiving a read clock signal, said first read clock signal line being coupled to a second read clock signal line of a second plurality of memory devices in a second memory module;
• a command signal line for receiving commands;
• and
• a flag signal line for receiving a flag signal from said memory controller, said flag signal line being coupled to said first and second pluralities of memory devices, wherein the flag signal causes the first and second pluralities of memory devices to output data corresponding to a previously accepted command received on the command signal line beginning at a predetermined number of read clock cycles after receipt of the flag signal by said memory controller.

A computer system comprising:

• a processor;
• a memory controller coupled to the processor;
• at least one memory module coupled to the memory controller, each of said at least one memory module having at least one set of memory devices, each of said at least one set of memory devices further comprising:
• a flag generation logic, and
• a plurality of memory devices, wherein each of said memory devices comprises,
• a read clock signal line for receiving a read clock signal, said read clock signal line being coupled to read clock signal lines of other corresponding memory devices on others of the at least one memory module;
• at least one command signal line for receiving commands;
• at least one data signal line coupled to said memory array;
• and
• a flag signal line coupled to said flag generation logic for receiving a flag signal,
• wherein the flag signal causes the memory device to output data on said data signal line corresponding to a previously accepted command received on the command signal line, beginning at a predetermined number of read clock cycles after receipt of the flag signal by the flag generation logic.

A method of operating a memory device coupled to a memory controller, a read clock signal source, and a flag signal source, comprising:

• receiving a command from the memory controller;
• receiving a flag signal from the flag signal source;
• receiving a read clock signal from the read clock signal source;
• outputting a data associated with the command synchronized with the read clock signal and beginning at a predetermined number of read clock cycles after receiving the flag signal.

A memory device comprising:

• a memory array;
• a control circuit;
• a read clock signal line coupled to said control circuit at a first terminal for receiving a read clock signal, said read clock signal line coupled to said control circuit at a second terminal for returning said read clock signal to said control circuit;
• a flag signal line coupled to said control circuit at a third terminal for receiving a flag signal, said flag signal line coupled to said to said control circuit at a fourth terminal for returning said flag signal to said control circuit, said flag signal line and said read clock signal line being routed so as to have equivalent signal propagation times.