Dynamic data amplifier with built-in voltage level shifting
AssigneeMosel Vitelic, Inc.
InventorJohn D. Heightley
Life of this patent
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Abstract
A read data latch circuit that provides a level shift between internal and external voltages that does not require added circuitry dedicated to equalizing or level shifting the data latch nodes. Data lines are provided having a higher capacitance than the capacitance of the data latch nodes. The data latch nodes are connected to the data lines through a switch. When the switch is open, an equalization charge is shared between the data lines and the latch nodes. The voltage for providing the equalization charge and data signals internal to the chip is lower than the data output signals provided to external circuitry by the data latch.
Claims31
In a data memory circuit, a method for level shifting first and second bit data signals for output on first and second latch nodes of a latching circuit having a first and second capacitance, respectively, comprising:
- providing a first data line, having a greater capacitance than said first capacitance, for selective connection to the first latch node;
- providing a second data line, having a greater capacitance than said second capacitance, for selective connection to the second latch node;
- isolating the first and second data lines from the respective first and second latch nodes;
- selectively connecting said latching circuit to first and second voltage sources, said first voltage being of magnitude being greater than the magnitude of said second voltage;
- equalizing said first and second data lines to a third voltage magnitude, said third voltage being less than said first voltage magnitude and greater than said second voltage;
- disconnecting said latching circuit from said first and second voltage sources;
- connecting said first and second latch nodes to said first and second data lines, respectively;
- and
- providing said first and second bit data signals to said first and second latch nodes, and
- disconnecting said first and second latch nodes from said first and second data lines, and
- connecting said latch to said first and second voltage sources and driving one of said first and second latch nodes to said first voltage magnitude greater than said third voltage magnitude and driving the other of said first and second latch nodes to a second voltage magnitude less than said third voltage magnitude, based upon the relative magnitudes of said first and second bit data signals.
A dynamic data amplifier having a built-in voltage level shifter for a data latch receiving bit data signals, comprising:
- at least a first data line having a first capacitance and charged to an equalized voltage level;
- a latching circuit having a first data latch node having a first node capacitance that is less than said first capacitance;
- a first switching device for selectively connecting and disconnecting said first data line to said first data latch node for charging said first latch node to approximately said equalized voltage level and for isolating the data latch from said first data line;
- a first voltage supply for driving said first data latch node to a voltage magnitude greater than said equalized voltage level based upon said received bit data signals;
- and
- a second switching device for selectively connecting and disconnecting said latching circuit from said first voltage supply.
A data latch circuit for providing an output signal representative of a bit of memory, said circuit comprising:
- a pre-charge circuit having a voltage source of a first voltage magnitude selectively connectable to first and second data lines each of an approximate first capacitance;
- a latch having first and second latch nodes each of an approximate second capacitance that is less than said first capacitance, said latch being selectively connected to a second voltage source having a magnitude greater than the magnitude of said first voltage source and being selectively connected to a third voltage source having a magnitude less than said first voltage magnitude for driving one of said latch nodes to a voltage higher than said first voltage magnitude and the other one of said latch nodes to a voltage less than said first voltage magnitude,
- a first switch circuit for selectively connecting said first and second data lines to said first and second latch nodes, respectively;
- and
- a second switch circuit for selectively connecting said latch to said second and third voltage sources.
In a semiconductor memory having a plurality of memory cells, a data read method including the steps of coupling, via a sense amplifier, local read data lines, and a pair of global data read lines, data signals representing stored data from a selected memory cell to a data read latch having a power supply voltage of magnitude greater than a memory supply voltage magnitude at which the sense amplifier, local, and global data read lines operate, and latching for output on a data latch node a HIGH voltage signal of a magnitude greater than a semiconductor memory supply voltage magnitude, the improvement comprising:
- before said data signals are coupled to said data read latch, equalizing said pair of global data read lines by operating an equalizing transistor having a path of controllable conductivity coupled therebetween and a path of controllable conductivity coupled to said memory supply voltage,
- isolating said data read latch circuit from its power supply and ground connections and connecting the data latch nodes of said latch circuit to said pair of global data read lines for receiving said data signals and for shifting the common mode level of said data latch nodes to the memory supply voltage level;
- equalizing and level shifting data latch nodes in the data read latch by operating first and second pass transistors each having a path of controllable conductivity coupled between a said global data read line and a corresponding data latch node,
- wherein the capacitance of each said data latch node is smaller than the capacitance of each corresponding global read line.
In a semiconductor memory having a supply voltage of a first magnitude, a plurality of memory cells, a sense amplifier, local read data lines, a pair of global data read lines, a data read latch coupled selectively to said global data read lines, said data read latch having a pair of latch nodes, the semiconductor memory also receiving a second voltage, said second voltage being associated with the data read latch, wherein the second voltage has a second magnitude greater than said first magnitude, the method comprising:
- level shifting and equalizing voltages at said latch nodes of said data read latch to said first voltage magnitude by charge sharing between said latch nodes and said data read lines,
- said data read lines having previously been precharged and equalized to said first voltage magnitude.
A semiconductor memory, comprising:
- first and second global data lines for processing in parallel first and second data signals representative of bit data;
- a pre-charge and equilibrate circuit coupled to said first and second global data lines;
- first and second isolation switches for controllably connecting said first and second global data lines to a data latch having first and second data latch nodes;
- a first voltage source of a first magnitude for selectively pre-charging both global data lines;
- a second voltage source for driving one of said data latch nodes to a second magnitude greater than said first magnitude, based upon said first and second data signals;
- and
- third and fourth isolation switches for controllably connecting said data latch to said second voltage source and ground.
In a data memory circuit of the type having a first and second global data lines, a precharge and equalizing circuit coupled to the global data lines, a data read latch containing first and second latch nodes, first and second power supply voltages associated with the data read latch, and an intermediate power supply voltage which is intermediate in magnitude between the first and second power supply voltages and is associated with the precharge and equalizing circuit, the method comprising the steps of:
- in a first step, isolating said first and second latch nodes from said global data lines, and during said isolating, precharging and equalizing said global data lines to said intermediate voltage;
- in a second step, level shifting the first and second latch nodes by selectively coupling said precharged and equalized global data lines thereto, while disconnecting said first and second power supply voltages from said data read latch;
- and
- in a third step, applying data from a memory cell to at least one of the precharged and equalized global data lines, to develop a voltage differential on said global data lines and on said latch nodes, and then latching said data read latch by selectively applying said first and second power supply voltages to said data read latch while isolating said global data lines from said data read lines, thereby driving said first and second latch nodes to said first and second power supply voltages.
In a data memory circuit of the type having a first and second global data lines, a precharge and equalizing circuit coupled to the global data lines, a data read latch containing first and second latch nodes, first and second power supply voltages associated with the data read latch, and an intermediate power supply voltage which is intermediate in magnitude between the first and second power supply voltages and is associated with the precharge and equalizing circuit, the method comprising the steps of:
- isolating said first and second latch nodes from said first and second power supply voltages;
- selectively coupling said first and second latch nodes to global data lines which have been precharged and equalized to said intermediate voltage, thereby to level shift the latch nodes substantially to said intermediate voltage;
- and then
- coupling said latch to said first and second power supply voltages and driving said latch nodes in accordance with a differential voltage developed on said global data line based on a memory cell.
Dependencies are inferred from the claim text.