Back to results
US 6,445,620 B2Granted
Flash memory cell for high efficiency programming
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Paul J. Rudeck, Chun Chen
Life of this patent
Estimating the term…
Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
Claims24
A method of erasing a flash memory cell comprising:
- applying a negative voltage to a gate region, the gate region formed in a common substrate of the flash memory cell along with a n-type drain region and a n-type source region, the n-type source region having a heavily doped arsenic region, the n-type source region surrounded by a heavily doped p type region;
- and
- applying a positive voltage to the n-type drain region.
A method of erasing a flash memory cell comprising:
- applying between about negative 8 volts and about negative 12 volts to a gate region, the gate region formed in a common substrate of the flash memory cell along with a n-type drain region and a n-type source region, the n-type source region having a heavily doped arsenic region, the n-type source region surrounded by a heavily doped p type region;
- and
- applying between about positive 4 volts and about positive 6 volts to the n-type drain region.
A method of erasing a flash memory cell comprising:
- applying between about negative 16 volts and about negative 20 volts to a gate region, the gate region formed in a common substrate of the flash memory cell along with a n-type drain region and a n-type source region, the n-type source region having a heavily doped arsenic region, the n-type source region surrounded by a heavily doped p type region;
- and
- applying between about positive 4 volts and about positive 6 volts to the n-type drain region.
A method of erasing a flash memory cell comprising:
- applying a negative voltage to a gate region, the gate region formed in a common substrate of the flash memory cell along with a n-type drain region and a n-type source region, the n-type source region having a heavily doped arsenic region, the n-type source region surrounded by a heavily doped p type region;
- applying a positive voltage to the n-type drain region;
- and
- maintaining a floating potential to the n-type source region.
1 more element
A method of erasing a flash memory cell comprising:
- applying a negative voltage to a gate region, tbe gate region formed in a common substrate of the flash memory cell along with a drain region and a source region, the drain region having a heavily doped arsenic region surrounded by a phosphorous region, the drain region abutting a lightly doped p type region, the source region having a heavily doped arsenic region surrounded by a heavily doped p type region;
- and
- applying a positive voltage to the drain region.
A method of erasing a flash memory cell comprising:
- applying a negative voltage to a gate regions the gate region formed in a common substrate of the flash memory cell along with a drain region and a source region, the drain region and the source region formed in a p-type well that surrounds the flash memory cell;
- and
- applying a positive voltage to the p type well.
A flash memory cell comprising:
- a source region, the source region having an arsenic region surrounded by a heavily doped boron region;
- a drain region, the drain region having an arsenic region surrounded by a phosphorous region, the drain region abutting a lightly doped boron region;
- a channel region, the channel region having a surfaces, the surface extending from the source region to the drain region;
- and
- a gate region formed in a common substrate with the source region, the drain region, and the channel region, wherein the flash memory cell is capable of being erased by applying a negative voltage to the gate region and applying a positive voltage to the drain region.
2 more elements
A flash memory cell comprising:
- a source region, the source region having an arsenic region surrounded by a heavily doped boron region;
- a drain region, the drain region having an arsenic region surrounded by a phosphorous region, the drain region abutting a lightly doped boron region;
- a channel region, the channel region having a surface, the surface extending from the source region to the drain region;
- and
- a gate region formed in a common substrate with the source region, the drain region, and the channel region, wherein the flash memory cell is capable of being erased by applying between about negative 8 volts and about negative 12 volts to the gate region and applying between about positive 4 volts and about positive 6 volts to the drain region.
2 more elements
A flash memory cell comprising:
- a source region, the source region having an arsenic region surrounded by a heavily doped boron region;
- a drain region, the drain region having an arsenic region surrounded by a phosphorous region, the drain region abutting a lightly doped boron region;
- a channel region, the channel region having a surface, the surface extending from the source region to the drain region, and
- a gate region formed in a common substrate with the source region, the drain region, and the channel region, wherein the flash memory cell is capable of being erased by applying between about negative 16 volts and about negative 20 volts to the gate region and applying between about positive 4 volts and about positive 6 volts to the drain region.
1 more element
A flash memory cell comprising:
- a source region, the source region having an arsenic region surrounded by a heavily doped boron region;
- a drain region, the drain region having an arsenic region surrounded by a phosphorous region, the drain region abutting a lightly doped boron region;
- a channel region the channel region having a surface, the surface extending from the source region to the drain region, the channel region having a heavily boron doped buried channel;
- and
- a stack, the stack formed in a common substrate with the source region, the drain region, and the channel region, the stack comprising a gate region, a gate dielectric, a floating gate, and an oxide layer, wherein the flash memory cell is capable of being erased by applying a negative voltage to the gate region and applying a positive voltage to the drain region.
2 more elements
Dependencies are inferred from the claim text.