Channel-erase nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsShigeru Atsumi, Tadayuki Taura, Toru Tanzawa
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Abstract
In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.
Claims10
A semiconductor memory device comprising:
- a memory cell array divided into blocks, each of said blocks including memory cells, word lines and bit lines being connected to these memory cells, and a row decoder for selecting said word lines;
- a first decoder for supplying the voltage supplied to said word lines to said row decoder;
- a second decoder for supplying a substrate voltage to a substrate in which said memory cells are formed;
- a first switch circuit which is connected between a first node to which said substrate voltage is supplied and a second node to which the voltage on said word line is supplied, said first and second nodes being connected to each other via a parasitic capacitance;
- a second switch circuit which is connected between said second node and the output terminal of said first decoder;
- and
- a third switch circuit which is connected between said first node and the output terminal of said second decoder.
Dependencies are inferred from the claim text.