Accelerated testing method and circuit for non-volatile memory
AssigneeMacronix International Co., Ltd.
InventorsWen-Jer Tsai, Nian-Kai Zous, Ta-Hui Wang
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Abstract
An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.
Claims4
An accelerated testing method for a non-volatile memory, comprising the steps of:
- selecting a threshold voltage variation standard for assessment;
- applying a set of negative gate bias voltages to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result;
- finding a curve relating lifetime and negative gate bias voltage according to the test result;
- and
- finding the lifetime of the non-volatile memory according to the threshold voltage variation standard.
A non-volatile memory quality-testing circuit for testing a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged into rows and columns with each row coupled to a word line driver and each column coupled to a bit line bias circuit, the quality-testing circuit comprising:
- a word line negative gate bias voltage generator coupled to the word line driver for applying a set of negative gate bias voltages to the gate terminals of programmed memory cells and conducting an accelerated testing.
A non-volatile memory having a quality-testing circuit therein, comprising:
- a memory cell array having a plurality of memory cells arranged into a plurality of rows and columns;
- a word line driving circuit coupled to various rows for driving each row;
- a bit line bias circuit coupled to various columns for driving each column;
- and
- a word line negative gate bias voltage generator coupled to the word line driver for applying a set of negative gate bias voltages to the gate terminals of programmed memory cells and conducting an accelerated testing.
Dependencies are inferred from the claim text.