Method and arrangement for preconditioning in a destructive read memory

Method for preconditioning a storage capacitor of a dynamic random access memory (DRAM) for a subsequent write operation, said storage capacitor being accessed by a wordline of said DRAM, said method comprising:

• activating said wordline to begin clearing any previously stored state of said storage capacitor;
• preconditioning said storage capacitor to a preconditioned voltage level immediately thereafter while maintaining said wordline activated;
• and
• deactivating said wordline.

Method for refreshing a storage capacitor of a dynamic random access memory (DRAM) to assist readiness for a subsequent write operation, said storage capacitor being accessed by a wordline of said DRAM and currently storing a voltage ranging from about preconditioned voltage level to a high state voltage level (“1”), said method comprising:

• activating said wordline to read a state currently stored in said storage capacitor, said state being a voltage ranging from about preconditioned voltage level to high state (‘1”), said state being read as a high state (“1”);
• preconditioning said storage capacitor to a preconditioned voltage level immediately thereafter while maintaining said wordline activated;
• deactivating said wordline;
• activating said wordline again during a writeback cycle thereafter to store said high state (‘1”) read from said storage capacitor back to said storage capacitor again, such that said storage capacitor is refreshed to high state (“1”), said storage capacitor at high state being ready to be written during a subsequent write cycle.

A dynamic random access memory (DRAM), comprising:

• a wordline driver controllable to selectively vary the duration of wordline activation;
• a wordline coupled to said wordline driver;
• a bitline coupled to said wordline by a transistor controlled by said wordline;
• a bitline restore device controllable to clamp said bitline to a first voltage level at a selected time,
• such that said wordline driver extends said duration of wordline activation during a preconditioning cycle in which said bitline at first is not clamped, and is later clamped by said bitline restore device to precondition a storage capacitor accessed by said wordline and said bitline to a preconditioned voltage level, and said wordline driver does not extend said duration of wordline activation during a subsequent write cycle, during which write cycle said bitline is not clamped.