Variable voltage isolation gate and method

A method of operating a memory cell in a memory device, the memory cell being coupled to an isolation transistor, the method comprising:

• accessing a memory cell by applying the isolation gate voltage wherein the isolation gate voltage is held approximately at a reference voltage;
• sensing the memory cell while keeping the isolation gate voltage at approximately the reference voltage;
• and
• raising the isolation gate voltage above the reference voltage by at least approximately an amount of a threshold voltage while restoring the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage.

A method of operating a memory cell in a memory device, the memory cell being coupled to an isolation transistor, the method comprising:

• holding an isolation gate voltage above a reference voltage by at least approximately the amount of the threshold voltage when accessing the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage;
• lowering the isolation gate voltage during sensing of the memory cell;
• and
• raising the isolation gate voltage above the reference voltage by at least approximately the amount of the threshold voltage while restoring the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage.

A method of operating a memory cell in a memory device, the memory cell being coupled to an isolation transistor, the method comprising:

• holding an isolation gate voltage above a reference voltage when accessing the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage;
• lowering the isolation gate voltage to approximately ground potential during sensing of the memory cell;
• and
• raising the isolation gate voltage above the reference voltage by at least approximately an amount of a threshold voltage while restoring the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage.

A method of operating a memory cell in a memory device, the memory cell being coupled to an isolation transistor, the method comprising:

• raising an isolation gate voltage above a reference voltage while restoring the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage;
• raising the isolation gate voltage above a reference voltage when accessing the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage;
• and
• lowering the isolation gate voltage during sensing of the memory cell.

A method of operating a memory cell, the memory cell being coupled to an isolation transistor, the method comprising:

• raising an isolation gate voltage above a reference voltage by at least approximately an amount of a threshold voltage while restoring the memory cell, while maintaining substantially all other memory device voltages at or below the reference voltage;
• accessing a memory cell by applying the isolation gate voltage wherein the isolation gate voltage is held approximately at the reference voltage;
• and
• sensing the memory cell while keeping the isolation gate voltage at approximately the reference voltage.