US 6,445,609 B2 · Integrated DRAM memory cell and DRAM memory

Abstract

A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another. To achieve, with increasing miniaturization of the DRAM memory patterns, during the transition from so-called “folded” bit line architectures to so-called “open” bit line architectures that the bit line grid, and thus also the grid of corresponding read/write amplifiers, varies linearly in scale with the longitudinal extent (L) of the memory cells (51), it is provided according to the invention that the bit lines (55) are now oriented perpendicularly to the longitudinal extent (L) of the memory cells (51) in the direction of the lateral extent (B) of the memory cells (51)

Claims16

Dependent claims

A DRAM memory having a plurality of memory cells that form at least one memory cell field, each memory cell of said plurality of memory cells being connected with a word line and a bit line, said memory cell comprising:

a memory capacitor;
and
a selection transistor that includes a gate, said memory capacitor and said selection transistor being formed in a region of an essentially rectangular cell area that is larger in a longitudinal direction in comparison with a width direction, word lines and bit lines of said plurality of memory cells being guided over each respective memory cell, said bit line being oriented substantially perpendicular to a longitudinal extension of said respective memory cell in a direction of a width extension of said memory cell, said work lines forming a first word line and a second word line, a plurality of gates of neighboring memory cells being connected over a respective first word line in a form of an island, said first word line being connected with a corresponding second overlying word line in a predetermined distance, said second word line being oriented substantially parallel to said longitudinal extension of said memory cell.

Dependencies are inferred from the claim text.

Integrated DRAM memory cell and DRAM memory

Life of this patent

Integrated DRAM memory cell and DRAM memory

Life of this patent

Abstract

Claims16